Young-Soo Sohn

发表

Rotating compensator spectroscopic ellipsometry for line-width control

Ha-Young Lee, Kyoung-Yoon Bang, Jaeho Lee, 2002, SPIE Advanced Lithography.

A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme

Hong-June Park, Soo-In Cho, Changhyun Kim, 2002 .

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM

Dong-Hun Lee, Kiho Kim, Yong-Ho Cho, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Refractive index change during exposure for 193-nm chemically amplified resists

Hye-Keun Oh, Eun-Mi Lee, Young-Soo Sohn, 1999, Advanced Lithography.

Fully On-Chip Current Controlled Open-Drain Output Driver for High-Bandwidth DRAMs

Jin-Hyeok Choi, Hong-June Park, Jae-Kyung Wee, 1999 .

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel

Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park, 2010, IEEE Custom Integrated Circuits Conference 2010.

Temperature rising effect of 193-nm chemically amplified resist during postexposure bake

Hye-Keun Oh, Eun-Mi Lee, Young-Soo Sohn, 2000, Advanced Lithography.

An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits

Jae-Yoon Sim, Hong-June Park, Seung-Jun Bae, 2012, 2012 International SoC Design Conference (ISOCC).

Analysis of the relation between exposure parameters and critical dimension by response surface model

Hye-Keun Oh, Heungin Bak, Young-Soo Sohn, 2001, SPIE Advanced Lithography.

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

MEMS-based method of polymer bead handling for chemical array sensors

Dean P. Neikirk, Yoon Sok Park, Young-Soo Sohn, 2005, SPIE Microtechnologies.

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Jae-Joon Song, Kyung-Soo Kim, Jongmin Kim, 2018, 2018 IEEE Symposium on VLSI Circuits.

Directional immobilization of antibody in a SPR sensor using EDC-activated protein A

Young-Soo Sohn, Yeon Kyung Lee, Jeong-Ok Lim, 2013, Other Conferences.

Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board

Jeong-Cheol Lee, Hong-June Park, Soo-In Cho, 2001 .

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Junha Lee, Jung-Hwan Choi, Joon-Young Park, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

LUSH-based SPR sensor for the detection of alcohols and pheromone

Young-Soo Sohn, Hui-Chong Lau, Yeon-Kyung Lee, 2013, Other Conferences.

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface

Jae-Yoon Sim, Hong-June Park, Young-Sik Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 20GB/s 256MB DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

Hoon Lee, Soo-In Cho, Jung-Hwan Choi, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

High-speed links for memory interface

Seon-Kyoo Lee, Jae-Yoon Sim, Young-Soo Sohn, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation

Hong-June Park, Seung-Jun Bae, Young-Soo Sohn, 2004 .

A 1.35Gbps decision feedback equalizing receiver for the SSTL SDRAM interface with 2X oversampling phase detector for skew compensation between clock and data

Hong-June Park, Seung-Jun Bae, Young-Soo Sohn, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

Empirical equations on electrical parameters of coupled microstrip lines with one side exposed to air

Jeong-Cheol Lee, Hong-June Park, Soo-In Cho, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

Hong-June Park, Soo-In Cho, Young-Soo Sohn, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Jae-Hyung Lee, Young-Hyun Jun, Dae-Hyun Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Empirical equations for electrical parameters of coupled microstrip lines with one side exposed to air

Hong-June Park, Soo-In Cho, Young-Soo Sohn, 1999 .

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.

Design and fabrication of a vibration sensor using a conductive ball

Yong-Soo Cho, Sie-Young Choi, Young-Soo Sohn, 2007, Microelectron. J..

A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise

Hong-June Park, Seung-Jun Bae, Hyung-Joon Chi, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Jae-Wook Lee, Reum Oh, Dong-Hak Shin, 2016, ISSCC.

Resist develop prediction by Monte Carlo simulation

Hye-Keun Oh, Young-Soo Sohn, Dong-Soo Sohn, 2002, SPIE Advanced Lithography.

A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation

Hong-June Park, Soo-In Cho, Seung-Jun Bae, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Yong-Jun Kim, Young-Sik Kim, Ju-Hwan Kim, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Hyun-Soo Park, Hyuk-Jun Kwon, Kyungbae Park, 2019, IEEE Journal of Solid-State Circuits.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

Disposable smart microfluidic-based biochips for clinical diagnostics

Joseph H. Nevin, Jin-Woo Choi, Young-Soo Sohn, 2001, 2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497).

An Analytic Time Jitter Equation of NRZ Signals in Uniformly Loaded PCB Transmission Lines

Soo-In Cho, Hyung-Gu Park, Young-Soo Sohn, 2001 .

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Young-Hyun Jun, Dong-Min Kim, Young-Sik Kim, 2010, 2010 Symposium on VLSI Circuits.

CD prediction by threshold energy resist model (TERM)

Jun-Taek Park, Hye-Keun Oh, Young-Soo Sohn, 2002, SPIE Advanced Lithography.

A Temperature- and Supply-Insensitive Fully On-Chip 1 Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs

Hong-June Park, Jae-Kyung Wee, Jong-Doo Joo, 2002 .

Modification of development parameters of 193-nm chemically amplified resist with pattern density

Han-Ku Cho, Hye-Keun Oh, Nakgeuon Seong, 2001, SPIE Advanced Lithography.

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Hoon Shin, Young Choi, Inkyu Moon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Jae-Yoon Sim, Hong-June Park, Seung-Jun Bae, 2011, IEEE Journal of Solid-State Circuits.

A 5.0Gbps/pin packet-based DRAM with low latency receiver and process insensitive PLL

Soo-In Cho, Jung-Hwan Choi, Byung-Chul Kim, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

Full-swing CMOS output driver using on-chip capacitors, with fast rise time and small overshoot

Hong-June Park, Jae-Yoon Sim, Young-Soo Sohn, 2001 .

Field emission characteristics of an oxidized porous polysilicon field emitter using the electrochemical oxidation process

Yong-Soo Cho, Sie-Young Choi, Young-Soo Sohn, 2006, Microelectron. J..

A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

Soo-In Cho, Jung-Hwan Choi, In-Young Chung, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

Photoresist thickness variation due to local and global topography

Woo-Sung Han, Hye-Keun Oh, Jin-Young Kim, 2001, SPIE Advanced Lithography.

Soft bake effect in 193-nm chemically amplified resist

Hye-Keun Oh, Eun-Mi Lee, Young-Soo Sohn, 2000, Advanced Lithography.

840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-processer communication

Hong-June Park, Jae-Yoon Sim, Soo-In Cho, 1999 .

Data processing device, system and method

Kwang-Il Park, Young-Soo Sohn, Dong-Min Kim, 2011 .

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Reum Oh, Dong-Hak Shin, Jae-Hun Jung, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Enhancing resolution of a miniaturized surface plasmon resonance sensor using bimetallic-based chip

Kyeong Seok Lee, Young-Soo Sohn, Won Mok Kim, 2013, Other Conferences.

A Temperature- and Supply-Insensitive 1Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs

Jin-Hyeok Choi, Jae-Kyung Wee, Young-Hee Kim, 2001 .

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2011, IEEE Journal of Solid-State Circuits.

Liquid flow through an array-based chemical sensing system

Dean P. Neikirk, John T. McDevitt, Eric V. Anslyn, 2000, SPIE MOEMS-MEMS.

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

Jae-Yoon Sim, Hong-June Park, Seung-Jun Bae, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond

Yuhwan Ro, Kyomin Sohn, Kwang-Il Park, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

Industry's First 7.2 Gbps 512GB DDR5 Module

Young-Soo Sohn, Tae-Young Oh, Gong-Heum Han, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

Study on Protein (IgG) Adsorption in Terms of Surface Modification of Cyclic Olefin Copolymer (COC) for Protein Biochip

Young-Soo Sohn, Junhai Kai, Chong H. Ahn, 2002 .

Protein Array Patterning on Cyclic Olefin Copolymer (COC) for Disposable Protein Chip

Young-Soo Sohn, Junhai Kai, Chong H. Ahn, 2004 .

Selected Peer-Reviewed Articles from the 8th Asian Conference on Chemical Sensors (ACCS 2009)

Hyung-Gi Byun, Wan-Young Chung, Young-Soo Sohn, 2011 .

Parameter extraction for 193 nm chemically amplified resist from refractive index change

Hye-Keun Oh, Ilsin An, Young-Soo Sohn, 2001 .

Characteristics of a Label-Less Electrochemical Immunosensor Based on a Field-Effect Transistor for the Detection of a Biomarker in Urine

Young-Soo Sohn, Sie-Young Choi, Chang-Kyu Kim, 2009 .

A disposable plastic biochip cartridge with on-chip power sources for blood analysis

Joseph H. Nevin, Young-Soo Sohn, Aniruddha Puntambekar, 2003, The Sixteenth Annual International Conference on Micro Electro Mechanical Systems, 2003. MEMS-03 Kyoto. IEEE.

Enhancing performance of a miniaturized surface plasmon resonance sensor in the reflectance detection mode using a waveguide-coupled bimetallic chip

Young-Soo Sohn, Won Mok Kim, Yeon Kyung Lee, 2013, Nanoscale Research Letters.

Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

A microbead array chemical sensor using capillary-based sample introduction: toward the development of an "electronic tongue".

John T McDevitt, Young-Soo Sohn, Eric V Anslyn, 2005, Biosensors & bioelectronics.

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

Jae-Yoon Sim, Hong-June Park, Soo-In Cho, 1999 .

Photoresist Exposure Parameter Extraction From Refractive Index Change During Exposure

Hye-Keun Oh, Ilsin An, Young-Soo Sohn, 1998, Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135).

Waveguide-coupled bimetallic film for enhancing the sensitivity of a surface plasmon resonance sensor in a fixed-angle mode

Young-Soo Sohn, Won Mok Kim, Yeon Kyung Lee, 2013 .

Detection of C-reactive protein using BioFET and extended gate

Young-Soo Sohn, Sang-Kwon Lee, Y. Sohn, 2007 .

Characteristics of 193 nm chemically amplified resist during post exposure bake and post exposure delay

Hye-Keun Oh, Young-Soo Sohn, Moon-Gyu Sung, 1999 .