Jafar Savoj

A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

Vassili Kireev, Hiep Pham, Daniel Wu, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

Ali M. Niknejad, Parag Upadhyaya, Ken Chang, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Device aware high-speed transceiver design in planar and FinFet technologies

Yohan Frans, Parag Upadhyaya, Ken Chang, 2014, 2014 IEEE International Electron Devices Meeting.

Clock and Data Recovery Circuits

Jafar Savoj, 2008 .