Charles Njinda

SIESTA: a multi-facet scan design system

Melvin A. Breuer, Sridhar Narayanan, Rajesh Gupta, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

SWiTEST: a switch level test generation system for CMOS combinational circuits

Melvin A. Breuer, Kuen-Jong Lee, Charles Njinda, 1992, DAC '92.

Optimal Seguencing of Scan Registers

Melvin A. Breuer, Sridhar Narayanan, Charles Njinda, 1992, Proceedings International Test Conference 1992.

Efficient testing of clock regenerator circuits in scan designs

Charles Njinda, Robert F. Molyneaux, Robert Bailey, 1997, DAC.

A hierarchical DFT architecture for chip, board and system test/debug

Charles Njinda, 2004, 2004 International Conferce on Test.

Performance driven BIST technique for random logic

Charles Njinda, Neeraj Kaul, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

How seriously do you take possible-detect faults?

Charles Njinda, Robert F. Molyneaux, Rajesh Raina, 1997, Proceedings International Test Conference 1997.

Extraction of a High­level Structural Representation from Circuit Descriptions with Applications to DFT/BIST "Lambda

Melvin A. Breuer, Charles Njinda, Ishwar Parulkar, 1994, 31st Design Automation Conference.

Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware

Melvin A. Breuer, Charles Njinda, Debaditya Mukherjee, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing

Melvin A. Breuer, Charles Njinda, Rajagopalan Srinivasan, 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

A systematic approach for designing testable VLSI circuits

Melvin A. Breuer, Charles Njinda, Sen-Pin Lin, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.