Michel Renovell

发表

Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies

Amit Karel, Florence Azaïs, Mariane Comte, 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

Testing the interconnect networks and I/O resources of field programmable analog arrays

Antonio Andrade, Marcelo Lubaszewski, Florence Azaïs, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Resistive Bridge fault model evolution from conventional to ultra deep submicron

Bernd Becker, Jean Marc Gallière, Michel Renovell, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

System-in-Package, a Combination of Challenges and Solutions

Michel Renovell, Philippe Cauvet, Serge Bernard, 2007, 12th IEEE European Test Symposium (ETS'07).

ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator

Florence Azaïs, Mariane Comte, Michel Renovell, 2008, VLSI Design.

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI -- LVT and RVT Configurations

Amit Karel, Florence Azaïs, Michel Renovell, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure

Florence Azaïs, Mariane Comte, Michel Renovell, 2004, J. Electron. Test..

A high accuracy triangle-wave signal generator for on-chip ADC testing

Michel Renovell, Serge Bernard, Florence Azaïs, 2002, Proceedings The Seventh IEEE European Test Workshop.

Accurate and efficient analytical electrical model of antenna for NFC applications

Mariane Comte, Michel Renovell, Vincent Kerzerho, 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing

Bernd Becker, Michel Renovell, Sandip Kundu, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A-to-D converters static error detection from dynamic parameter measurement

Florence Azaïs, Mariane Comte, Michel Renovell, 2003, Microelectron. J..

Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC

Florence Azaïs, Michel Renovell, Philippe Cauvet, 2007, IET Comput. Digit. Tech..

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream

Michel Renovell, Peter Zipf, Manfred Glesner, 2002, Lecture Notes in Computer Science.

Principe et Problèmatique pour le Test des System-0n-Chip

Michel Renovell, 2004 .

Testing the configurable analog blocks of field programmable analog arrays

Antonio Andrade, Marcelo Lubaszewski, Florence Azaïs, 2004, 2004 International Conferce on Test.

Electrical Behavior of GOS Faults in Domino Logic

Mariane Comte, Michel Renovell, Satoshi Ohtake, 2005 .

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST

Florence Azaïs, Michel Renovell, Serge Bernard, 2001, VLSI-SOC.

Testing for floating gates defects in CMOS circuits

Michel Renovell, Andre Ivanov, S. Rafiq, 1998 .

Novel technique for testing FPGAs

Yervant Zorian, Cecilia Metra, Michel Renovell, 1998, Proceedings Design, Automation and Test in Europe.

The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults

Bernd Becker, Michel Renovell, Piet Engelke, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC

Florence Azaïs, Mariane Comte, Michel Renovell, 2007, 12th IEEE European Test Symposium (ETS'07).

The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault

Michel Renovell, Yves Bertrand, P. Huc, 1996, EDCC.

A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters

Pascal Nouet, Marcelo Lubaszewski, Florence Azaïs, 2005, J. Electron. Test..

New implementions of predictive alternate analog/RF test with augmented model redundancy

Mariane Comte, Michel Renovell, Vincent Kerzerho, 2014, DATE 2014.

A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs

Michel Renovell, Yves Bertrand, M. Ildevert, 1992, The Fifth International Conference on VLSI Design.

Analog BIST generator for ADC testing

Florence Azaïs, Michel Renovell, Serge Bernard, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Built-in self-test of global interconnects of field programmable analog arrays

Marcelo Lubaszewski, Michel Renovell, Tiago R. Balen, 2005, Microelectron. J..

TI-BIST: a temperature independent analog BIST for switched-capacitor filters

Luigi Carro, Marcelo Lubaszewski, Florence Azaïs, 2000, Proceedings of the Ninth Asian Test Symposium.

2009 27th IEEE VLSI Test Symposium

Masayuki Arai, Bernd Becker, Kazumi Hatayama, 2009 .

Testing the configurable analog blocks of field programmable analog arrays

Florence Azaïs, Michel Renovell, Tiago R. Balen, 2004 .

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect

Amit Karel, Florence Azaïs, Mariane Comte, 2016, 2016 17th Latin-American Test Symposium (LATS).

A methodology and design for effective testing of voltage-controlled oscillators (VCOs)

Florence Azaïs, Michel Renovell, Yves Bertrand, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2006, J. Electron. Test..

Mitigating read & write errors in STT-MRAM memories under DVS

Elena I. Vatajelu, Michel Renovell, Rosa Rodríguez-Montañés, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Modeling and Detectability of Full Open Gate Defects in FinFET Technology

Victor Champac, Michel Renovell, Hector Villacorta, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

New implementions of predictive alternate analog/RF test with augmented model redundancy

Florence Azaïs, Mariane Comte, Michel Renovell, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Multi-Mode Signature Analyzer for Analog and Mixed Circuits

Salvador Mir, Marcelo Lubaszewski, Florence Azaïs, 1997 .

Functional Testing of Processor Cores in FPGA-Based Applications

Michel Renovell, Franc Novak, Anton Biasizzo, 2009, Comput. Informatics.

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges

Bernd Becker, Jürgen Schlöffel, Michel Renovell, 2007, 16th Asian Test Symposium (ATS 2007).

Sram cell stability metric under transient voltage noise

Elena I. Vatajelu, Michel Renovell, Joan Figueras, 2014, Microelectron. J..

Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric

Elena I. Vatajelu, Michel Renovell, Joan Figueras, 2011, 2011 Asian Test Symposium.

A DFT Technique to Improve ATPG Efficiency for Sequential Circuits

Michel Renovell, Yves Bertrand, Frédéric Bancel, 1993, The Sixth International Conference on VLSI Design.

On the Synthesis of Analog Cascaded Filters with Optimal Test Point Insertion

Pascal Nouet, Marcelo Lubaszewski, Florence Azaïs, 2003 .

Investigations on alternate analog/RF test with model redundancy

Mariane Comte, Michel Renovell, Serge Bernard, 2014 .

A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing

Florence Azaïs, Mariane Comte, Michel Renovell, 2013 .

Towards an ADC BIST scheme using the histogram test technique

Michel Renovell, Serge Bernard, Florence Azaïs, 2000, Proceedings IEEE European Test Workshop.

Experimental test infrastructure supporting IEEE 11494 Standard

Pascal Nouet, Florence Azaïs, Michel Renovell, 2002 .

Test escapes: analysis of short defect

Michel Renovell, Yves Bertrand, F. Azdis, 1999, Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387).

Guest Editorial

José Luis Huertas, Michel Renovell, Adoración Rueda, 2005, J. Electron. Test..

A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs

Florence Azaïs, Mariane Comte, Michel Renovell, 2006, IEEE Design & Test of Computers.

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

Florence Azaïs, Michel Renovell, Serge Bernard, 2003, J. Electron. Test..

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

Bernd Becker, Mariane Comte, Michel Renovell, 2008, 2008 13th European Test Symposium.

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Testing the configurable interconnect/logic interface of SRAM-based FPGA's

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1999, DATE '99.

An Automatic Tool for Generation of ADC BIST Architecture

Florence Azaïs, Mariane Comte, Michel Renovell, 2003 .

Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systems

Mariane Comte, Michel Renovell, Serge Bernard, 2016, Impedance Spectroscopy.

Hardware resource minimization for histogram-based ADC BIST

Florence Azaïs, Michel Renovell, Serge Bernard, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies

Amit Karel, Florence Azaïs, Mariane Comte, 2017, J. Electron. Test..

Influence of parasitic memory effect on single-cell faults in SRAMs

Michel Renovell, Said Hamdioui, Zaid Al-Ars, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs

Michel Renovell, 2003, J. Circuits Syst. Comput..

A New FPGA for DSP Applications Integrating BIST Capabilities

Luigi Carro, Marcelo Lubaszewski, Michel Renovell, 2004, J. Electron. Test..

Message from the Technical Program Chairs

Abbes Amira, Michel Renovell, Adam Osseiran, 2006, ISCC.

Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

Manfred Glesner, Michel Renovell, Peter Zipf, 2002 .

BIST of delay faults in the logic architecture of symmetrical FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Delay Testing Viability of Gate Oxide Short Defects

Florence Azaïs, Jean Marc Gallière, Michel Renovell, 2005, Journal of Computer Science and Technology.

Testing Challenges for Modern FPGAs

Michel Renovell, M. Renovell, 2008 .

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects

Bernd Becker, Mariane Comte, Michel Renovell, 2009, 2009 27th IEEE VLSI Test Symposium.

Microsystems Testing: A Challenge

Michel Renovell, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Defect analysis for delay-fault BIST in FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008

Marcelo Lubaszewski, Michel Renovell, Rajesh Gupta, 2008, SBCCI.

On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring

Florence Azaïs, Michel Renovell, Yves Bertrand, 2008, 2008 14th IEEE International On-Line Testing Symposium.

On-chip signature analyser for analogue circuit testing

Florence Azaïs, Michel Renovell, Yves Bertrand, 1996 .

Minimizing the number of test configurations for different FPGA families

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

DTIS 2014 foreword

Giorgio Di Natale, Paolo Prinetto, Michel Renovell, 2014, DTIS.

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

Florence Azaïs, Michel Renovell, Serge Bernard, 2001, J. Electron. Test..

The multi-configuration: A DFT technique for analog circuits

Florence Azaïs, Michel Renovell, Yves Bertrand, 1996, Proceedings of 14th VLSI Test Symposium.

Optimized implementations of the multi-configuration DFT technique for analog circuits

Florence Azaïs, Michel Renovell, Yves Bertrand, 1998, Proceedings Design, Automation and Test in Europe.

Testing for gate oxide short defects using the detectability interval paradigm

Florence Azaïs, Mariane Comte, Jean Marc Gallière, 2014, it Inf. Technol..

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

Amit Karel, Florence Azaïs, Mariane Comte, 2019, J. Electron. Test..

A multi-mode stimuli generator for analogue and mixed-signal built-in-self-test

Marcelo Lubaszewski, Florence Azaïs, Michel Renovell, 1998 .

Smart selection of indirect parameters for DC-based alternate RF IC testing

Florence Azaïs, Mariane Comte, Michel Renovell, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

International Conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS 2006)

Patrick Girard, Mohamed Masmoudi, Michel Renovell, 2006 .

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC

Florence Azaïs, Mariane Comte, Michel Renovell, 2006, Eleventh IEEE European Test Symposium (ETS'06).

The Transient Reponse Analysis Method Applied to the Test of Field Programmable Analog Arrays: Feasibility Study

Marcelo Lubaszewski, Michel Renovell, Tiago R. Balen, 2005 .

Hard to Detect Bridging Defects in a Cross-Point Digital Switch

Alfredo Benso, Michel Renovell, Yves Bertrand, 2003 .

On the Efficiency of Measuring ADC Dynamic Parameters to Detect ADC Static Errors

Florence Azaïs, Mariane Comte, Michel Renovell, 2003 .

A Specific Test Methodology for Symmetric SRAM-Based FPGAs

Michel Renovell, M. Renovell, 2000, FPL.

Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology

Amit Karel, Mariane Comte, Michel Renovell, 2017, IEEE Transactions on Nanotechnology.

Proceedings of the 21st annual symposium on Integrated circuits and system design

Rajesh Gupta, Marcelo Lubaszewski, Michel Renovell, 2008 .

SRAM-Based FPGAs: Testing the Embedded RAM Modules

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1999, J. Electron. Test..

High quality TPG for delay faults in look-up tables of FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Spot defect modeling: Past and evolution

Michel Renovell, 2017, 2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Optimal conditions for Boolean and current detection of floating gate faults

Florence Azaïs, Michel Renovell, Yves Bertrand, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Multiconfiguration technique to reduce test duration for sequential circuits

Michel Renovell, Yves Bertrand, Frédéric Bancel, 1993, Proceedings of IEEE International Test Conference - (ITC).

Testing the unidimensional interconnect architecture of symmetrical SRAM-based FPGA

Yervant Zorian, Paolo Prinetto, Michel Renovell, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Analysis of the Specification Influence on the Efficiency of an Optimized Test Flow for ADCs

Florence Azaïs, Mariane Comte, Michel Renovell, 2003 .

From dependable computing systems to computing for integrated dependable systems?

Jacob A. Abraham, Hans-Dieter Kochs, Michel Renovell, 1998, Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224).

Guest Editorial

Michel Renovell, 2001, J. Electron. Test..

Low voltage testing for interconnect opens under process variations

Michel Renovell, Víctor H. Champac, Jesus Moreno, 2012, 2012 13th Latin American Test Workshop (LATW).

A new methodology for realistic open defect detection probability evaluation under process variations

Michel Renovell, Víctor H. Champac, Jesus Moreno, 2011, 29th VLSI Test Symposium.

Simulating Resistive-Bridging and Stuck-At Faults

Bernd Becker, Michel Renovell, Piet Engelke, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy

Florence Azaïs, Mariane Comte, Michel Renovell, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

A multi-configuration strategy for an application dependent testing of FPGAs

Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short

Florence Azaïs, Jean Marc Gallière, Michel Renovell, 2003, J. Electron. Test..

International Conference on Embedded Systems & Critical Applications

Michel Robert, Michel Renovell, Samir Ben Ahmed, 2008 .

Parasitic memory effect in CMOS SRAMs

Michel Renovell, Zaid Al-Ars, Sandra Irobi, 2010, 2010 5th International Design and Test Workshop.

Models for Bridging Defects

Florence Azaïs, Michel Renovell, Joan Figueras, 2010 .

Modeling feedback bridging faults with non-zero resistance

Bernd Becker, Michel Renovell, Ilia Polian, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

Solutions for the self-adaptation of communicating systems in operation

Salvador Mir, Michel Renovell, Haralampos-G. D. Stratigopoulos, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

Fault modelisation of external shorts in CMOS circuits

Michel Renovell, Yves Bertrand, P. Huc, 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

A new DFT technique to reduce test duration for sequential circuits

Michel Renovell, Y. Bertrand, F. Bancel, 1993, Proceedings ETC 93 Third European Test Conference.

Current testing in dynamic CMOS circuits

Michel Renovell, Joan Figueras, 1995, J. Electron. Test..

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator

J. Jiang, Florence Azaïs, Mariane Comte, 2013, 2013 22nd Asian Test Symposium.

A design-for-test technique for multistage analog circuits

Florence Azaïs, Michel Renovell, Yves Bertrand, 1995, Proceedings of the Fourth Asian Test Symposium.

A Model for Resistive Open Recursivity in CMOS Random Logic

Bernd Becker, Michel Renovell, Ilia Polian, 2008 .

Electrical behavior of GOS fault affected domino logic cell

Hideo Fujiwara, Mariane Comte, Michel Renovell, 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC

Mariane Comte, Michel Renovell, V. Kerzerho, 2006 .

Testing for floating gates defects in CMOS circuits

André Ivanov, Michel Renovell, Sassan Tabatabaei, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

A multi-converter DFT technique for complex SIP: Concepts and validation

Mariane Comte, Michel Renovell, Philippe Cauvet, 2009, 2009 European Conference on Circuit Theory and Design.

Modeling gate oxide short defects in CMOS minimum transistors

Jean Marc Gallière, Michel Renovell, Florence Azaïs, 2002, Proceedings The Seventh IEEE European Test Workshop.

An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions

Florence Azaïs, Michel Renovell, Yves Bertrand, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

RAM-based FPGAs: a test approach for the configurable logic

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1998, Proceedings Design, Automation and Test in Europe.

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

Jean Marc Gallière, Michel Renovell, Víctor H. Champac, 2018, Journal of electronic testing.

A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio

Michel Renovell, Yves Bertrand, P. Huc, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique de Fin d'Année)

Christian Landrault, Florence Azaïs, Michel Renovell, 2002 .

Timing Defect Analysis in Look-Up Tables of SRAM-Based FPGAs

Serge Pravossoudovitch, Olivier Heron, Michel Renovell, 2003 .

Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies

Florence Azaïs, Mariane Comte, Michel Renovell, 2015, Microelectron. J..

Applying the Oscillation Test Strategy to FPAA’s Configurable Analog Blocks

Marcelo Lubaszewski, Florence Azaïs, Michel Renovell, 2005, J. Electron. Test..

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST

Florence Azaïs, Michel Renovell, Serge Bernard, 2001, J. Electron. Test..

An approach to the built-in self-test of field programmable analog arrays

Antonio Andrade, Marcelo Lubaszewski, Florence Azaïs, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Serial transistor network modeling for bridging fault simulation

Michel Renovell, Yves Bertrand, P. Huc, 1995, Proceedings of the Fourth Asian Test Symposium.

Delay testing of MOS transistor with gate oxide short

Florence Azaïs, Jean Marc Gallière, Michel Renovell, 2003, 2003 Test Symposium.

TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année

Giorgio Di Natale, Arnaud Virazel, Alberto Bosio, 2010 .

Digital Test Method for Embedded Converters with Unknown-Phase Harmonics

Florence Azaïs, Mariane Comte, Michel Renovell, 2011, J. Electron. Test..

BISTing switched-current circuits

Florence Azaïs, Michel Renovell, Yves Bertrand, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds

Michel Renovell, Yves Bertrand, P. Huc, 1994, EDCC.

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges

Bernd Becker, Michel Renovell, Ilia Polian, 2007 .

Automatic test pattern generation for resistive bridging faults

Bernd Becker, Michel Renovell, Ilia Polian, 2004 .

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1998, FPL.

Implementation of an Experimental IEEE 1149.4 Mixed-Signal Test Chip

Pascal Nouet, Florence Azaïs, Michel Renovell, 2002 .

Structural Testing of Modern Reconfigurable Chips

Michel Renovell, 2003 .

Functional and structural testing of switched-current circuits

Michel Renovell, Florence Azaïs, Yves Bertrand, 1999, European Test Workshop 1999 (Cat. No.PR00390).

Different experiments in test generation for XILINX FPGAs

Yervant Zorian, Michel Renovell, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Scan Design and Secure Chip

Michel Renovell, Bruno Rouzeyre, Marie-Lise Flottes, 2004, IOLTS.

On the detectability of CMOS floating gate transistor faults

André Ivanov, Florence Azaïs, Michel Renovell, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors

Florence Azaïs, Mariane Comte, Michel Renovell, 2004, J. Electron. Test..

Analog built-in saw-tooth generator for ADC histogram test

Florence Azaïs, Michel Renovell, Yves Bertrand, 2002 .

Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation

Marcelo Lubaszewski, Michel Renovell, Tiago R. Balen, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Bridging fault coverage improvement by power supply control

Michel Renovell, Yves Bertrand, P. Huc, 1996, Proceedings of 14th VLSI Test Symposium.

A low-cost adaptive ramp generator for analog BIST applications

Florence Azaïs, Michel Renovell, Serge Bernard, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays

Bernd Becker, J. Jiang, Florence Azaïs, 2013, 2013 14th Latin American Test Workshop - LATW.

A Novel DFT Technique to Test a Complete Set of ADC's and DAC's Embedded in a Complex SiP

Mariane Comte, Michel Renovell, Philippe Cauvet, 2006 .

Test pattern and test configuration generation methodology for the logic of RAM-based FPGA

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Test de Circuits et de Systèmes Intégrés

Christian Landrault, Florence Azaïs, Michel Renovell, 2004 .

On-chip analog output response compaction

Florence Azaïs, Michel Renovell, Yves Bertrand, 1997, Proceedings European Design and Test Conference. ED & TC 97.

ASimulatorofSmall-DelayFaultsCausedbyResistive-OpenDefects

Michel Renovell, Ilia Polian, P. Engelke, 2008 .

SRAM-based FPGA's: testing the interconnect/logic interface

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology

Amit Karel, Florence Azaïs, Mariane Comte, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Toward Adaptation of ADCs to Operating Conditions through On-chip Correction

Florence Azaïs, Mariane Comte, Michel Renovell, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

Marcelo Lubaszewski, Michel Renovell, Tiago R. Balen, 2007, J. Electron. Test..

Revisiting the classical fault models through a detailed analysis of realistic defects

Michel Renovell, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Testing the Local Interconnect Resources of SRAM-Based FPGA's

Yervant Zorian, Michel Renovell, Jean Michel Portal, 2000, J. Electron. Test..

Behavior and test of open-gate defects in FinFET based cells

Michel Renovell, Víctor H. Champac, Hector Villacorta, 2016, 2016 21th IEEE European Test Symposium (ETS).

Reuse of existing resources for analog BIST of a switch capacitor filter.

Luigi Carro, Marcelo Lubaszewski, Florence Azaïs, 2000, DATE '00.

International TestConference 2008 Technical Program Committee

Abhijit Chatterjee, Kenneth M. Butler, Cecilia Metra, 2008 .

Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions

Amit Karel, Florence Azaïs, Mariane Comte, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Boolean and current detection of MOS transistor with gate oxide short

Florence Azaïs, Jean Marc Gallière, Michel Renovell, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Automatic test pattern generation for resistive bridging faults

Bernd Becker, Michel Renovell, Piet Engelke, 2004, Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004).

Functional test of field programmable analog arrays

Marcelo Lubaszewski, Michel Renovell, Tiago R. Balen, 2006, 24th IEEE VLSI Test Symposium.

CMOS bridging fault modeling

Michel Renovell, Yves Bertrand, P. Huc, 1994, Proceedings of IEEE VLSI Test Symposium.

SRAM stability metric under transient noise

Michel Renovell, Álvaro Gómez Pau, Joan Figueras Pàmies, 2012 .

Detection of Defects Using Fault Model Oriented Test Sequences

Florence Azaïs, Michel Renovell, Yves Bertrand, 1999, J. Electron. Test..

Testing for Realistic Spot Defects in CMOS Technology: a Unified View

Michel Renovell, 2006 .

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Michel Renovell, Víctor H. Champac, Jesus Moreno, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFT

Michel Renovell, Sattar Mirzakuchaki, Zainalabedin Navabi, 2007 .

A new methodology for adc test flow optimization

Florence Azaïs, Mariane Comte, Michel Renovell, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Realistic Fault Models for Defects in Electronic Circuits

Michel Renovell, 2004 .

Combining Functional and Structural Approaches for Switched-Current Circuit Testing

Florence Azaïs, Michel Renovell, Yves Bertrand, 2000, J. Electron. Test..

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family

Yervant Zorian, Michel Renovell, Jean Michel Portal, 2000, J. Electron. Test..

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

Florence Azaïs, Mariane Comte, Michel Renovell, 2013, Microelectron. J..

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell

Elena I. Vatajelu, Paolo Prinetto, Michel Renovell, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Self-Adaptive NFC Systems

Michel Renovell, Serge Bernard, Florence Azaïs, 2014 .

Analyzing the test generation problem for an application-oriented test of FPGAs

Michel Renovell, Y. Zorian, Joan Figueras, 2000, Proceedings IEEE European Test Workshop.

The concept of resistance interval: a new parametric model for realistic resistive bridging fault

Michel Renovell, Yves Bertrand, P. Huc, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Test strategy sensitivity to defect parameters

Michel Renovell, Yves Bertrand, 1997, Proceedings International Test Conference 1997.

Making predictive analog/RF alternate test strategy independent of training set size

Florence Azaïs, Mariane Comte, Michel Renovell, 2012, 2012 IEEE International Test Conference.

A structural test methodology for SRAM-based FPGAs

Michel Renovell, 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

Editorial

Patrick Garda, Michel Renovell, Serge Bernard, 2014, Microelectron. J..

Testing the Interconnect of RAM-Based FPGAs

Yervant Zorian, Michel Renovell, Jean Michel Portal, 1998, IEEE Des. Test Comput..

An IR-Drop Simulation Principle Oriented to Delay Testing

Michel Renovell, Ilia Polian, Yves Bertrand, 2012 .

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications

Florence Azaïs, Mariane Comte, Michel Renovell, 2005, J. Electron. Test..

The Scalable and Reconfigurable DFT for Embedded A/MS Cores

Michel Renovell, Sattar Mirzakuchaki, Zainalabedin Navabi, 2006 .

A Discussion on Test Pattern Generation for FPGA—Implemented Circuits

Yervant Zorian, Michel Renovell, Jean Michel Portal, 2001, J. Electron. Test..

Implementation of a linear histogram BIST for ADCs

Florence Azaïs, Michel Renovell, Serge Bernard, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

TOF: a tool for test pattern generation optimization of an FPGA application oriented test

Yervant Zorian, Michel Renovell, Jean Michel Portal, 2000, Proceedings of the Ninth Asian Test Symposium.

Integrated test assembly for an analog-digital converter and corresponding method

Florence Azaïs, Michel Renovell, Yves Bertrand, 2000 .

SIP Test Architectures

Michel Renovell, Philippe Cauvet, Serge Bernard, 2008 .

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements

Florence Azaïs, Mariane Comte, Michel Renovell, 2014, Microelectron. J..

Design-for-testability for switched-current circuits

Florence Azaïs, Michel Renovell, Yves Bertrand, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

An all-digital DFT scheme for testing catastrophic faults in PLLs

André Ivanov, Florence Azaïs, Michel Renovell, 2003, IEEE Design & Test of Computers.

Power-aware voltage tuning for STT-MRAM reliability

Elena I. Vatajelu, Paolo Prinetto, Stefano Di Carlo, 2015, 2015 20th IEEE European Test Symposium (ETS).

Analysis and attenuation proposal in ground bounce

Florence Azaïs, Michel Renovell, Víctor H. Champac, 2004, 13th Asian Test Symposium.

B-open: A New Defect in Nanometer Technologies due to SADP Process

Victor Champac, Michel Renovell, Freddy Forero, 2019, 2019 IEEE European Test Symposium (ETS).

Current testing viability in dynamic CMOS circuits

Michel Renovell, Joan Figueras, 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Session details: Keynote

Michel Renovell, 2008, SBCCI '08.

Conditions pour le Test de Pannes de Délai des Look-Up Table dans les FPGA à Base de SRAM

Olivier Heron, Michel Renovell, Patrick Girard, 2008 .

Improving Defect Detection in Static-Voltage Testing

Florence Azaïs, Michel Renovell, Yves Bertrand, 2002, IEEE Des. Test Comput..

A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells

Jean Marc Gallière, Michel Renovell, Víctor H. Champac, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Automatic Test Pattern Generation for Resistive Bridging Faults

Bernd Becker, Michel Renovell, Piet Engelke, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS

Michel Renovell, Joan Figueras Pàmies, Elena I. Vatajelu, 2010 .

Editorial

Mohamed Masmoudi, Michel Renovell, Mohamed Masmoudi, 2010, Microelectron. J..

Test of RAM-based FPGA: methodology and application to the interconnect

Yervant Zorian, Michel Renovell, Joan Figueras, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Simulating Resistive-Bridging and Stuck-At Faults

Bernd Becker, Michel Renovell, Piet Engelke, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Implementing model redundancy in predictive alternate test to improve test confidence

Florence Azaïs, Mariane Comte, Michel Renovell, 2013, 2013 18th IEEE European Test Symposium (ETS).

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008

Michel Renovell, Milos Drutarovsky, Bernd Straube, 2008, DDECS.

Electrical analysis and modeling of floating-gate fault

Michel Renovell, Gaston Cambon, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fundamentals of System Testing: Challenges for System-On-Chips

Michel Renovell, 2004 .

Automatic Generation of LH-BIST Architecture for ADC Testing

Florence Azaïs, Michel Renovell, Serge Bernard, 2003 .

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2005, J. Electron. Test..

Extending IEEE Std. 1149.4 analog boundary modules to enhance mixed-signal test

Pascal Nouet, Florence Azaïs, Michel Renovell, 2003, IEEE Design & Test of Computers.

Fast and Fully-Efficient Test Flow for ADCs

Florence Azaïs, Mariane Comte, Michel Renovell, 2005 .

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing

Florence Azaïs, Mariane Comte, Michel Renovell, 2014, 2014 15th Latin American Test Workshop - LATW.

IS-FPGA : a new symmetric FPGA architecture with implicit scan

Yervant Zorian, Michel Renovell, Jean Michel Portal, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Realistic fault model for external shorts in MOS technologies

Michel Renovell, Yves Bertrand, P. Huc, 1993 .

Viability of a Delay Testing of Gate Oxide Short Transistors

Florence Azaïs, Michel Renovell, Yves Bertrand, 2005 .

Analysis of short defects in FinFET based logic cells

Jean Marc Gallière, Michel Renovell, Víctor H. Champac, 2017, Latin American Test Symposium.

Estimating Static Parameters of A-to-D Converters from Spectral Analysis

Marcelo Lubaszewski, Florence Azaïs, Mariane Comte, 2002 .

A compact DC model of gate Oxide short defect

R. Bouchakour, Florence Azaïs, Michel Renovell, 2004 .