Y. Bonhomme

Efficient scan chain design for power minimization during scan testing under routing constraint

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Design of routing-constrained low power scan chains

P. Girard, C. Landrault, S. Pravossoudovitch, 2004 .

WIRELESS SENSOR AND ACTOR NETWORKS II

Wael Abd-Almageed, Mohamed Eltoweissy, Hervé Guyennet, 2008 .

Programmable extended SEC-DED codes for memory errors

Valentin Gherman, Fabrice Auzanneau, Yannick Bonhomme, 2011, 29th VLSI Test Symposium.

System-level hardware-based protection of memories against soft-errors

Valentin Gherman, Mickael Cartron, Yannick Bonhomme, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Memory Reliability Improvement Based on Maximized Error-Correcting Codes

V. Gherman, S. Evain, Y. Bonhomme, 2013, Journal of electronic testing.

Memory reliability improvements based on maximized error-correcting codes

Valentin Gherman, Yannick Bonhomme, Samuel Evain, 2012, 2012 17th IEEE European Test Symposium (ETS).

Generalized parity-check matrices for SEC-DED codes with fixed parity

Valentin Gherman, Yannick Bonhomme, Samuel Evain, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing

Patrick Girard, Yannick Bonhomme, P. Girard, 2005, Journal of Low Power Electronics.