Naga Durga Prasad Avirneni

Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning

Viswanathan Subramanian, Arun K. Somani, Mikel Bezdek, 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs

Arun K. Somani, Naga Durga Prasad Avirneni, 2012, IEEE Trans. Computers.

Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems

Viswanathan Subramanian, Arun K. Somani, Naga Durga Prasad Avirneni, 2009, 2009 IEEE/IFIP International Conference on Dependable Systems & Networks.

Managing contamination delay to improve Timing Speculation architectures

Arun K. Somani, Prem Kumar Ramesh, Naga Durga Prasad Avirneni, 2016, PeerJ Comput. Sci..

Managing contamination delay to improve Timing Speculation architectures

Arun K. Somani, Prem Kumar Ramesh, Naga Durga Prasad Avirneni, 2016, PeerJ Prepr..

Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors

Arun K. Somani, Prem Kumar Ramesh, Naga Durga Prasad Avirneni, 2016, IEEE Transactions on Computers.

Countering Power Analysis Attacks UsingReliable and Aggressive Designs

Arun K. Somani, Naga Durga Prasad Avirneni, Arun Kumar Somani, 2014, IEEE Transactions on Computers.

RAKSHA: Reliable and Aggressive frameworK for System design using High-integrity Approaches

Naga Durga Prasad Avirneni, N. D. Avirneni, 2012 .

Managing contamination delay to improve Timing Speculation architectures

Arun K. Somani, Prem Kumar Ramesh, Naga Durga Prasad Avirneni, 2015, PeerJ Prepr..