Bingfeng Mei

发表

Design style case study for computer nodes of a heterogeneous NoC platform

Diederik Verkest, Henk Corporaal, Geert Deconinck, 2004 .

Design style case study for embedded multi media compute nodes

Diederik Verkest, Henk Corporaal, Francky Catthoor, 2004, 25th IEEE International Real-Time Systems Symposium.

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

Bjorn De Sutter, Tom Vander Aa, Paul Coene, 2008, LCTES '08.

Architecture exploration for a reconfigurable architecture template

Rudy Lauwereins, Diederik Verkest, Andy Lambrechts, 2005, IEEE Design & Test of Computers.

A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Embedded Systems

Patrick Schaumont, Serge Vernalde, Bingfeng Mei, 2000 .

Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes

Will Moffat, Bingfeng Mei, Francisco-Javier Veredas, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware

Rudy Lauwereins, Hugo De Man, Yajun Ha, 2001, FPL.

Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

Bingfeng Mei, Bart Masschelein, Francisco-Javier Veredas, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

Bjorn De Sutter, Steven Dupont, Tom Vander Aa, 2008, J. Signal Process. Syst..

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2003, FPL.

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

Rudy Lauwereins, Diederik Verkest, Serge Vernalde, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2003, DATE.

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

Steven J. E. Wilton, Serge Vernalde, Bingfeng Mei, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hardware and a Tool Chain for ADRES

Bjorn De Sutter, Steven Dupont, Hong-Seok Kim, 2006, ARC.

Energy aware architecture exploration of a CGRA template

Diederik Verkest, Praveen Raghavan, Andy Lambrechts, 2005 .

A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots

Bjorn De Sutter, Tom Vander Aa, Bingfeng Mei, 2007, CASES '07.

Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor

Bjorn De Sutter, Mladen Berekovic, Andreas Kanstein, 2009, Microprocess. Microsystems.

Mapping MPEG Video Decoders on the ADRES Reconfigurable Array Processor for Next Generation Multi-Mode Mobile Terminals

Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, 2007 .

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Bjorn De Sutter, Osman Allam, Tom Vander Aa, 2010, J. Signal Process. Syst..