Y. Nishimichi

A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store

J. Miyake, T. Maeda, Y. Nishimichi, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

Takashi Taniguchi, Yoshiyuki Takagi, Y. Nishimichi, 1990 .

A 100 Mhz Embedded Risc Microcontroller

Toru Kakiage, Y. Nishimichi, H. Yamashita, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

An 8-kbit content-addressable and reentrant memory

J. Miyake, Y. Nishimichi, K. Kagawa, 1985, IEEE Journal of Solid-State Circuits.

An 8Kb content-addressable and reentrant memory

Y. Nishimichi, J. Miyake, H. Kodata, 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.