Michael Ruegg

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

Thomas Toifl, Martin L. Schmatz, Michael Ruegg, 2010, IEEE Journal of Solid-State Circuits.

Multi-Phase Generator PLL with 360° Digitally Programmable Phase Shift for 10Gb/s Serial Links

Thomas Toifl, Christian Menolfi, Marcel Kossel, 2005 .

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

Christian Menolfi, Andrea Prati, Matthias Braendli, 2012, IEEE Journal of Solid-State Circuits.

A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI

Thomas Toifl, Christian Menolfi, Matthias Braendli, 2011, 2011 IEEE International Solid-State Circuits Conference.

Refactoring towards seams in C++

Peter Sommerlad, Michael Ruegg, 2012, 2012 7th International Workshop on Automation of Software Test (AST).

A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch

Michael Ruegg, Sasan Cyrusian, Eva Tatschl-Unterberger, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

Thomas Toifl, Martin L. Schmatz, Michael Ruegg, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS

Thomas Toifl, Christian Menolfi, Andrea Prati, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology

Thomas Toifl, Martin L. Schmatz, Christian Menolfi, 2006, IEEE Journal of Solid-State Circuits.