Jhon-Jhy Liaw

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Sreedhar Natarajan, Shien-Yang Wu, Hung-Jen Liao, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Hidehiro Fujiwara, Po-Yi Huang, Jonathan Chang, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications

Jonathan Chang, Hung-Jen Liao, Ching-Wei Wu, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 16nm FinFET CMOS technology for mobile SoC and computing applications

Shien-Yang Wu, S. H. Yang, M. C. Chiang, 2013 .

A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

Jonathan Chang, Shien-Yang Wu, Hung-Jen Liao, 2014, IEEE Journal of Solid-State Circuits.

A 65nm node strained SOI technology with slim spacer

Chenming Hu, Tsai-Sheng Gau, Yee-Chia Yeo, 2003, IEEE International Electron Devices Meeting 2003.