C.A.J. van Eijk

发表

Formal verification of sequential circuits using binary decision diagrams

J. P. Veen, C.A.J. van Eijk, 1995 .

On the efficiency of learning techniques for combinational checking

Geert Janssen, C.A.J. van Eijk, G. Janssen, 1998 .

Constraint driven design space exploration for signal processing

C.A.J. van Eijk, 2000 .

Detection of equivalent state variables in finite state machine verification

C.A.J. van Eijk, J.A.G. Jess, J. Jess, 1995 .

BDD techniques to reduce switching activity in logic circuits

Michel Berkelaar, R. Tavares, J. P. Veen, 1999 .

A BDD-based verification engine for combinational equivalence checking

J. P. Veen, C.A.J. van Eijk, 1997 .

Register binding for DSP code containing predicated execution

Qin Zhao, C.A.J. van Eijk, 1999 .

Asynchronous counters for low power applications

C.A.J. van Eijk, J. W. J. M. Rutten, 1997 .

Formal verification of combinational circuits using binary decision diagrams

C.A.J. van Eijk, 1994 .

Towards the functional verification of large sequential circuits

C.A.J. van Eijk, J.A.G. Jess, 1997 .

Design of a prototype system behaviour simulator for IDaSS

C.A.J. van Eijk, 1992 .