J. Valls-Coquillat

发表

A symbol flipping decoder for NB-LDPC relying on multiple votes

David Declercq, Javier Valls-Coquillat, Francisco Garcia-Herrero, 2014, 2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC).

Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes

David Declercq, Javier Valls-Coquillat, Francisco Garcia-Herrero, 2019, Circuits Syst. Signal Process..

Time Synchronization for the IEEE 802.11a/g WLAN Standard

Javier Valls-Coquillat, Ma José Canet, José Marín-Roig, 2007, 2007 IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications.

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Javier Valls-Coquillat, Francisco Garcia-Herrero, Ma José Canet, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

50 Years of CORDIC: Algorithms, Architectures, and Applications

K. Sridharan, Koushik Maharatna, Javier Valls-Coquillat, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard

Javier Valls-Coquillat, Ma José Canet, Vicenç Almenar, 2007, 2007 15th European Signal Processing Conference.

Syndrome-based Min-sum vs OSD-0 decoders: FPGA Implementation and Analysis for Quantum LDPC codes

Nithin Raveendran, Francisco Garcia-Herrero, Javier Valls, 2021, IEEE Access.

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

T. Sansaloni, Javier Valls-Coquillat, Asuncion Perez-Pascual, 2009, J. Signal Process. Syst..

Design of an efficient digital down-converter for a SDR-based DVB-S receiver

Javier Valls-Coquillat, Asuncion Perez-Pascual, Vicenç Almenar, 2007, 2007 18th European Conference on Circuit Theory and Design.

Evaluation of CORDIC Algorithms for FPGA Design

Keshab K. Parhi, Javier Valls-Coquillat, Martin Kuhlmann, 2002, J. VLSI Signal Process..

Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications

Javier Valls-Coquillat, Roberto Gutierrez, J. Valls-Coquillat, 2009, J. Signal Process. Syst..

Implementation on FPGA of a LUT-Based atan(Y/X) Operator Suitable for Synchronization Algorithms

Javier Valls-Coquillat, Roberto Gutierrez, J. Valls-Coquillat, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

Javier Valls-Coquillat, Vicente Torres-Carot, Roberto Gutierrez, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes

Mark F. Flanagan, Javier Valls-Coquillat, Francisco Garcia-Herrero, 2012, IEEE Communications Letters.

Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers

Javier Valls, Eduardo Boemo, E. Boemo, 2003, IEEE Trans. Circuits Syst. II Express Briefs.

Fast FPGA-based pipelined digit-serial/parallel multipliers

T. Sansaloni, Javier Valls-Coquillat, Eduardo I. Boemo, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Design and FPGA implementation of digit-serial FIR filters

T. Sansaloni, J. Valls, M.M. Peiro, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree

Javier Valls-Coquillat, Francisco Garcia-Herrero, J. M. Català-Perez, 2014, IEEE Communications Letters.

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

Javier Valls-Coquillat, Fabian Angarita, Vicenç Almenar, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low latency T-EMS decoder for non-binary LDPC codes

David Declercq, Javier Valls-Coquillat, Francisco Garcia-Herrero, 2013, 2013 Asilomar Conference on Signals, Systems and Computers.

Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA

T. Sansaloni, Javier Valls-Coquillat, Asuncion Perez-Pascual, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

High-throughput FPGA-based emulator for structured LDPC codes

Javier Valls-Coquillat, Asuncion Perez-Pascual, Fabian Angarita, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation

Javier Valls-Coquillat, Fabian Angarita, José Marín-Roig, 2012, IET Commun..

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes

T. Sansaloni, Javier Valls-Coquillat, Asuncion Perez-Pascual, 2012, J. Signal Process. Syst..

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

T. Sansaloni, Javier Valls-Coquillat, Ma José Canet, 2012, J. Signal Process. Syst..

FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques

Javier Valls-Coquillat, Vicente Torres-Carot, Roberto Gutierrez, 2010, J. Syst. Archit..

A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation

M. Martinez-Peiro, J. Valls, T. Sansaloni, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).