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Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel

B. Haran, N. Loubet, K. Zhao, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

M. Belyansky, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Challenges and Opportunities for Stacked Transistor: DTCO and Device

A. Young, B. Haran, T. Hook, 2021, Symposium on VLSI Technology.

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

M. Khare, B. Haran, N. Loubet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Critical Elements for Next Generation High Performance Computing Nanosheet Technology

V. Narayanan, D. Guo, E. Leobandung, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).