Y. Kohno

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Yoichi Akasaka, H. Shinohara, S. Kayano, 1986 .

A 4 to 25 GHz 0.5 W monolithic lossy match amplifier

Y. Kohno, T. Takagi, Y. Itoh, 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

S. Kayano, H. Shinohara, Y. Kohno, 1987 .

A 45-ns 256K CMOS static RAM with a tri-level word line

T. Wada, H. Shinohara, K. Anami, 1985, IEEE Journal of Solid-State Circuits.

A 5‐ns 32 K ×8/×9 bi‐CMOS TTL SRAM with alternated bit line load architecture

Hiroki Honda, Tadashi Sumi, Masahiro Ishida, 1994 .

FAST 8K multiplied by 8 MIXED CMOS STATIC RAM.

Yoichi Akasaka, Tsutomu Yoshihara, Y. Kohno, 1985 .

A 4.5ns 256K CMOS SRAM with tri-level word line

Yoichi Akasaka, H. Shinohara, K. Ichinose, 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A fast 8K × 8 mixed CMOS static RAM

H. Shinohara, K. Anami, T. Yoshihara, 1985, IEEE Transactions on Electron Devices.

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

Shigenobu Maeda, Y. Kohno, K. Anami, 1999 .