Chengyong Wu

发表

How sensitive is processor customization to the workload's input datasets?

Stijn Eyerman, Lieven Eeckhout, Zheng Li, 2011, 2011 IEEE 9th Symposium on Application Specific Processors (SASP).

A low-cost memory interface for high-throughput accelerators

Jing Huang, Paolo Ienne, Olivier Temam, 2014, 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

A Register Allocation Framework for Banked Register Files with Access Constraints

Feng Zhou, Junchao Zhang, Zhaoqing Zhang, 2005, Asia-Pacific Computer Systems Architecture Conference.

Going vertical in memory management: Handling multiplicity by multi-policy

Lei Liu, Yong Li, Mingyu Chen, 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

SWAP: Parallelization through Algorithm Substitution

Lieven Eeckhout, Olivier Temam, Yang Chen, 2012, IEEE Micro.

A Small-Footprint Accelerator for Large-Scale Neural Networks

Junjie Liu, Dongsheng Wang, Olivier Temam, 2015, ACM Trans. Comput. Syst..

Finding representative sets of optimizations for adaptive multiversioning applications pdf

Grigori Fursin, Yang Chen, Chengyong Wu, 2009, ArXiv.

Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata

Lixia Liu, Roy Dz-Ching Ju, Chen Fu, 2004, J. Instr. Level Parallelism.

Pragma Directed Shared Memory Centric Optimizations on GPUs

Lei Liu, Jing Li, Yuan Wu, 2016, Journal of Computer Science and Technology.

Novel Iterative Channel Estimation Method for DTMB System

Guanghui Liu, You Lu, Chengyong Wu, 2012, 2012 IEEE 12th International Conference on Computer and Information Technology.

Evaluating iterative optimization across 1000 datasets

Lieven Eeckhout, Olivier Temam, Grigori Fursin, 2010, PLDI '10.

Practical Iterative Optimization for the Data Center

Lieven Eeckhout, Olivier Temam, Yang Chen, 2015, ACM Trans. Archit. Code Optim..

Efficient resource management during instruction scheduling for the EPIC architectures

Lixia Liu, Roy Dz-Ching Ju, Chen Fu, 2003, 2003 12th International Conference on Parallel Architectures and Compilation Techniques.

Elastic CGRAs

Paolo Ienne, Olivier Temam, Yunji Chen, 2013, FPGA '13.

A software memory partition approach for eliminating bank-level interference in multicore systems

Lei Liu, Mingyu Chen, Yungang Bao, 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

Identification of P2P traffic in campus network

Hui Lu, Chengyong Wu, 2010, 2010 International Conference on Computer Application and System Modeling (ICCASM 2010).

Iterative optimization for the data center

Lieven Eeckhout, Olivier Temam, Yang Chen, 2012, ASPLOS XVII.

Two-Level Task Scheduling for Irregular Applications on GPU Platform

Lei Liu, Jing Li, Yuan Wu, 2017, International Journal of Parallel Programming.

An Overview of the Open Research Compiler

Ruiqi Lian, Lixia Liu, Roy Dz-Ching Ju, 2004, LCPC.

Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators

Olivier Temam, Lingamneni Avinash, Krishna V. Palem, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems

Lei Liu, Yong Li, Mingyu Chen, 2014, TACO.

Transforming GCC into a research-friendly environment: plugins for optimization tuning and reordering, function cloning and program instrumentation

Grigori Fursin, Liang Peng, Yuriy Kashnikov, 2010 .

An Improved Clipping Scheme Based on TR for PAPR Reduction in OFDM Systems

Guanghui Liu, You Lu, Chengyong Wu, 2012, 2012 IEEE 12th International Conference on Computer and Information Technology.

The Ground Objects Identification for Digital Remote Sensing Image Based on the BP Neural Network

Tao Zhang, Jie Yuan, Chengyong Wu, 2014 .

Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators

Olivier Temam, Lingamneni Avinash, Krishna V. Palem, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach

Huawei Li, Lieven Eeckhout, Olivier Temam, 2014, TACO.

QE Modeling and Test Selection Based on PNFSM

Hua Li, Lingling Wang, Xinming Ye, 2009, 2009 5th International Conference on Wireless Communications, Networking and Mobile Computing.

Global Tiling for Communication Minimal Parallelization on Distributed Memory Systems

Lei Liu, Li Chen, Xiaobing Feng, 2008, Euro-Par.

DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning

Ninghui Sun, Zidong Du, Jia Wang, 2014, ASPLOS.

Deconstructing iterative optimization

Lieven Eeckhout, Olivier Temam, Grigori Fursin, 2012, TACO.

A High-Throughput Neural Network Accelerator

Jia Wang, Tianshi Chen, Olivier Temam, 2015, IEEE Micro.

BPM/BPM+: Software-based Memory Partitioning Mechanisms for Eliminating DRAM Bank-/Channel-level Interference in Multicore Systems

Lei Liu, Yong Li, Mingyu Chen, 2014 .

Neuromorphic accelerators: A comparison between neuroscience and machine-learning approaches

Lei Zhang, Tianshi Chen, Olivier Temam, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?

Lei Liu, Hao Yang, Yong Li, 2016, IEEE Transactions on Computers.

Optimizing Packet Accesses for a Domain Specific Language on Network Processors

Xiao-Feng Li, Lixia Liu, Tao Liu, 2005, LCPC.

Diva: A dataflow programming model and its runtime support in Java virtual machine

Bin Fan, Yang Chen, Lujie Zhong, 2008, 2008 13th Asia-Pacific Computer Systems Architecture Conference.

Retraining-based timing error mitigation for hardware neural networks

Huawei Li, Xiaowei Li, David Novo, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).