M. Ushiyama

A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM

H. Kume, M. Kato, T. Adachi, 1992, 1992 International Technical Digest on Electron Devices Meeting.

An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

T. Tanaka, Y. Ohji, M. Ushiyama, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

Sub-10-ps gate delay by reducing the current crowding effect at an extension

M. Ushiyama, J. Yugami, T. Shiba, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories

M. Ushiyama, H. Kume, N. Miyamoto, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.