M. Morino

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

H. Fujisawa, M. Nakamura, Y. Takai, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

H. Fujisawa, S. Narui, S. Miyatake, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

H. Fujisawa, Y. Takai, T. Matano, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

H. Fujisawa, M. Nakamura, Y. Takai, 2005, IEEE Journal of Solid-State Circuits.

A 29 ns 64 Mb DRAM with hierarchical array architecture

T. Takahashi, M. Morino, K. Komatsuzaki, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.