O. van der Straten

ZERO THICKNESS DIFFUSION BARRIERS AND METALLIZATION LINERS FOR NANOSCALE DEVICE APPLICATIONS

Alain E. Kaloyeros, Eric T. Eisenbraun, E. Eisenbraun, 2011 .

48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme

J. Kelly, C. Koay, Yunpeng Yin, 2013, 2013 IEEE International Interconnect Technology Conference - IITC.

Thermal and electrical barrier performance testing of ultrathin atomic layer deposition tantalum-based materials for nanoscale copper metallization

E. Eisenbraun, A. Kaloyeros, O. van der Straten, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Role of high aspect-ratio thin-film metal deposition in Cu back-end-of-line technology

A. Simon, D. Edelstein, T. Nogami, 2020 .

Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects

T. Standaert, K. Cheng, C. Penny, 2019, IEEE Electron Device Letters.

Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

M. Rasch, W. Haensch, V. Narayanan, 2021, IEEE Electron Device Letters.

First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications

D. Edelstein, R. Johnson, J. Slaughter, 2021, International Electron Devices Meeting.

A 14 nm Embedded STT-MRAM CMOS Technology

T. Standaert, D. Edelstein, R. Johnson, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).