Dmitri Mihhailov

发表

Hardware implementation of recursive sorting algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA).

Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

Hardware implementation of recursive algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Acceleration of Recursive Data Sorting over Tree-based Structures

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011 .

Processing N-ary trees in hardware circuits

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 International Symposium on Integrated Circuits.

Project-Oriented Approach to Low-Power Topics in Advanced Digital Design Course

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2010 .

Application-specific hardware accelerator for implementing recursive sorting algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Field-Programmable Technology.

Implementation in FPGA of Address-Based Data Sorting

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Address-based data processing over N-ary trees

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2013, Eurocon 2013.

Optimization of recursive sorting algorithms for implementation in hardware

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Microelectronics.

Performance evaluation for FPGA-based processing of tree-like structures

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

FSM decomposition with application to FPGA synthesis

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2009, CompSysTech '09.

Implementation of address-based data sorting on different FPGA platforms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2013, East-West Design & Test Symposium (EWDTS 2013).

FPGA platform based digital design education

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2008, CompSysTech.

Advanced topics of FSM design using FPGA educational boards and web-based tools

Margus Kruus, Alexander Sudnitson, Dmitri Mihhailov, 2010, 2010 East-West Design & Test Symposium (EWDTS).

High-performance hardware accelerators for sorting and managing priorities

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Recursion and hierarchy in digital design and prototyping: a case study

Margus Kruus, Valery Sklyarov, Iouliia Skliarova, 2011, CompSysTech '11.

Optimization of address-based data sorting unit with external memory support

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2013, CompSysTech '13.

Processing tree-like data structures for sorting and managing priorities

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 IEEE Symposium on Computers & Informatics.

EEG Analyzer prototype based on FPGA

Maksim Gorev, Peeter Ellervee, Hiie Hinrikus, 2011, 2011 7th International Symposium on Image and Signal Processing and Analysis (ISPA).

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

and Managing Priorities

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011 .

Multilevel models for data processing

Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, 2011, 2011 IEEE GCC Conference and Exhibition (GCC).

FPGA-Based Implementation of EEG Analyzer

Maksim Gorev, Peeter Ellervee, Maksim Jenihhin, 2010 .