M.B. Zahid

Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories

R. Degraeve, L. Breuil, J. Van Houdt, 2010, IEEE Electron Device Letters.

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

S. De Gendt, R. Degraeve, B. Kaczer, 2005, IEEE Electron Device Letters.

Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks

R. Degraeve, B. Kaczer, B. Govoreanu, 2008, 2008 IEEE International Electron Devices Meeting.