Lluís Terés

A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications

Francisco Serra-Graells, Josep Maria Margarit, German Vergara, 2015, IEEE Journal of Solid-State Circuits.

A calibration-free 96.6-dB-SNDR non-bootstrapped 1.8-V 7.9-mW delta-sigma modulator with class-AB single-stage switched VMAs

Francisco Serra-Graells, Stepan Sutula, Lluís Terés, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures

David Castells-Rufas, Jordi Carrabina, Jaume Joven, 2008, 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008).

Teaching mixed-mode full-custom VLSI design with gaf, SpiceOpus and Glade

Francisco Serra-Graells, Stepan Sutula, Jofre Pallares, 2014, 10th European Workshop on Microelectronics Education (EWME).

A 70-$\mu$ m Pitch 8-$\mu$ W Self-Biased Charge-Integration Active Pixel for Digital Mammography

Francisco Serra-Graells, Lluís Terés, Roger Figueras, 2011, IEEE Transactions on Biomedical Circuits and Systems.

A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers

Francisco Serra-Graells, Josep Maria Margarit, Lluís Terés, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A 10kfps 32×32 integrated test platform for electrical characterization of imagers

Enric Cabruja, Francisco Serra-Graells, Josep Maria Margarit, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Sub-μW fully programmable CMOS DPS for uncooled infrared fast imaging

Francisco Serra-Graells, Josep Maria Margarit, Lluís Terés, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A self-biased PLL-tuned AER pixel for high-speed infrared imagers

Francisco Serra-Graells, Josep Maria Margarit, Lluís Terés, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).