Matheus Gibiluka

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework

Matheus T. Moreira, Ney Laert Vilar Calazans, Matheus Gibiluka, 2015, 2015 Euromicro Conference on Digital System Design.

Design and analysis of the HF-RISC processor targeting voltage scaling applications

Sergio Bampi, Matheus T. Moreira, Sergio Johann Filho, 2016, 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI).

BAT-Hermes: A transition-signaling bundled-data NoC router

Fernando Gehm Moraes, Matheus T. Moreira, Ney Laert Vilar Calazans, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

BaBaNoC: An asynchronous network-on-chip described in Balsa

Matheus T. Moreira, Fabiano Hessel, Ney Laert Vilar Calazans, 2013, 2013 International Symposium on Rapid System Prototyping (RSP).

A standard cell characterization flow for non-standard voltage supplies

Matheus T. Moreira, Ney Laert Vilar Calazans, Walter Lau Neto, 2016, 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI).

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications

Peter A. Beerel, Matheus T. Moreira, Ney Laert Vilar Calazans, 2016, 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Blade -- A Timing Violation Resilient Asynchronous Template

Melvin A. Breuer, Zhichao Li, Peter A. Beerel, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

Analysis of voltage scaling effects in the design of resilient circuits

Matheus Gibiluka, 2016 .