J. Conner

A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

P. Abramowitz, J. Conner, M. Woo, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 /spl mu/m CMOS process

J. Conner, G. Braceras, J. Sousa, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors

J. Conner, S. Murphy, S. Venkatesan, 2006, 2006 International Electron Devices Meeting.

Dual-metal gate CMOS with HfO2 gate dielectric

P. Abramowitz, J. Conner, E. Luckowski, 2002, Digest. International Electron Devices Meeting,.

80 nm poly-Si gate CMOS with HfO/sub 2/ gate dielectric

J. Conner, S. Bagchi, L. Prabhu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Finfet with isolated n+ and p+ gate regions strapped with metal and polysilicon

J. Conner, A. Vandooren, B. E. White, 2003, 2003 IEEE International Conference on SOI.

Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions

J. Conner, A. Vandooren, S. Samavedam, 2003, IEEE Electron Device Letters.

Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

J. Conner, C. Mazure, S. Murphy, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..