O. Louveau

HF Vapor Release Assessment to Address NEMS Applications

Laurent Lachal, Sylvain Auclair, Pascal Lavios, 2008 .

Challenges of back end of the line for sub 65 nm generation

J. Cluzel, O. Louveau, M. Fayolle, 2003 .

Platinum silicide metallic source & drain process optimization for FDSOI pMOSFETs

M. Vinet, D. Lafond, F. Allain, 2009, 2009 IEEE International SOI Conference.

Integrating of Cu/SiOC in Cu dual damascene interconnect for 0.1-µm technology

Pascal Besson, Gilles L. Fanget, Lucile Arnaud, 2002 .

Three dimensional chip stacking using a wafer-to-wafer integration

N. Kernevez, M. Zussy, Zhihong Huang, 2007, 2007 IEEE International Interconnect Technology Conferencee.

Characterization of photoresist poisoning induced by a post etch stripping step

O. Louveau, N. Rochat, D. Louis, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Patterning issues in superconducting nanowire single photon detector fabrication

O. Louveau, Christophe Constancias, J. Villégier, 2007 .

Integration of Cu/SiOC in dual damascene interconnect for 0.1 /spl mu/m technology using a new SiC material as dielectric barrier

J. Cluzel, Lucile Arnaud, O. Louveau, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

Dry ashing process evaluation for porous ULK films

O. Louveau, G. W. Hills, D. Louis, 2004 .

Porous dielectric dual damascene patterning issues for 65 nm node: can architecture bring a solution?

O. Louveau, H. Feldis, M. Assous, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).