Yusuke Nitta

IEEE Symposium on Low-Power and High-Speed Chips

Josep Torrellas, Hideharu Amano, Masato Suzuki, 2011 .

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core

Tetsuya Yamada, Fumio Arakawa, Makoto Ishikawa, 2006, IEICE Trans. Electron..

Low-power design of 90-nm SuperH/spl trade/ processor core

Tetsuya Yamada, Fumio Arakawa, Makoto Ishikawa, 2005, 2005 International Conference on Computer Design.

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth

Takayasu Ito, Kenichi Osada, Tetsuya Yamada, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

Fumio Arakawa, Takahiro Irita, Tatsuya Kamei, 2004 .

Generation of a hierarchical representation for graphic patterns based on grouping

Jun'ichi Toyoda, Masato Soga, Masuzo Yanagida, 1993, Systems and Computers in Japan.

A 45nm 37.3GOPS/W heterogeneous multi-core SoC

Junichi Miyakoshi, Hironori Kasahara, Tetsuya Yamada, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Design methodology of a 200 MHz superscalar macroprocessor: SH-4

Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

Junichi Miyakoshi, Hironori Kasahara, Tetsuya Yamada, 2011, IEICE Trans. Electron..