S. Geissler

PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

C. Lichtenau, M.I. Ringler, T. Pfluger, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

C. Lichtenau, M.I. Ringler, T. Pfluger, 2005, IEEE Journal of Solid-State Circuits.

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

D. Kramer, S. Geissler, N. Rohrer, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A 64B CPU Pair: Dual- and Single-Processor Chips

C. Lichtenau, S. Geissler, R. Hilgendorf, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 580 MHz RISC microprocessor in SOI

D. Kramer, S. Geissler, N. Rohrer, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

The current-carrying corner inherent to trench isolation

S. Geissler, W. Haensch, D. Poindexter, 1993, IEEE Electron Device Letters.

A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

S. Geissler, P. Sandon, N. Rohrer, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).