Manoranjan Pradhan

发表

Implementation of Modular Multiplication for RSA Algorithm

Sushanta Kumar Sahu, Manoranjan Pradhan, 2011, 2011 International Conference on Communication Systems and Network Technologies.

Some studies of FPGA based design and implementation of RISC processor

Manoranjan Pradhan, 2011 .

Simulation and Verification of Self Test 16-Bit Processor

Manoranjan Pradhan, 2011 .

A High-Speed Booth Multiplier Based on Redundant Binary Algorithm

Ashish Panda, Manoranjan Pradhan, Ranjan Kumar Barik, 2018 .

Design of Conservative Gate and their Novel Application in Median Filtering in Emerging QCA Nanocircuit

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2018 .

A modified redundant binary adder for efficient VLSI architecture

Manoranjan Pradhan, Ranjan Kumar Barik, Ekta Prusty, 2016, 2016 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT).

An Improved Conversion Circuit for Redundant Binary to Conventional Binary Representation

Manoranjan Pradhan, Ranjan Kumar Barik, Snigdha Subhadarshinee Tripathy, 2017 .

Fast signed multiplier using Vedic Nikhilam algorithm

Manoranjan Pradhan, Satya Ranjan Sahu, Bandan Kumar Bhoi, 2020, IET Circuits Devices Syst..

Speed Comparison of 16x16 Vedic Multipliers

Rutuparna Panda, Manoranjan Pradhan, Rutuparna Panda, 2011 .

Novel Robust Design for Reversible Code Converters and Binary Incrementer with Quantum-Dot Cellular Automata

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2018 .

FPGA based implementation of 8-bit ALU of a RISC processor using Booth algorithm written in VHDL language

Manoranjan Pradhan, Paresh Kumar Pasayat, Bhupesh Kumar Pasayat, 2013 .

A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular Automata

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2019 .

ANOMALY DETECTION USING ARTIFICIAL NEURAL NETWORK

Sateesh Kumar Pradhan, Manoranjan Pradhan, Sudhir Kumar Sahu, 2012 .

Control Unit Design of a 16-bit Processor Using VHDL

Nilamani Bhoi, Manoranjan Pradhan, Alpesh Kumar Dauda, 2013 .

A Universal Reversible Gate Architecture for Designing N-Bit Comparator Structure in Quantum-dot Cellular Automata

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2017 .

FPGA Implementation of RSA Encryption System

Sushanta Kumar Sahu, Manoranjan Pradhan, 2011 .

Efficient ASIC and FPGA implementation of cube architecture

Manoranjan Pradhan, Ranjan Kumar Barik, 2017, IET Comput. Digit. Tech..

IMPLEMENTATION OF KARATSUBA ALGORITHM USING POLYNOMIAL MULTIPLICATION

Manoranjan Pradhan, Sudhanshu Mishra, 2012 .

Minimization of energy-holes By DBPC (Dynamic Bonding and Partitioning Coverage) in a WSN

Manoranjan Pradhan, Chinmaya Kumar Nayak, ManasRanjan Tripathy, 2015 .

Novel binary divider architecture for high speed VLSI applications

Manoranjan Pradhan, Bandan Kumar Bhoi, Ratiranjan Senapati, 2013, 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES.

Synthesis Methods of Baugh-Wooley Multiplier and Non-restoring Divider to Enhance Primitive’s Results of QCA Circuits

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2019 .

Design of magnetic dipole based 3D integration nano-circuits for future electronics application

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2018 .

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

Rutuparna Panda, Manoranjan Pradhan, Ranjan Kumar Barik, 2017, J. Circuits Syst. Comput..

Comparative Analysis of Partial Product Generators for Decimal Multiplication Using Signed-Digit Radix-10, -5 and -4 Encodings

Manoranjan Pradhan, Dharamvir Kumar, 2020 .

Cryptography on Graphics Processing Unit: A Survey

Manoranjan Pradhan, Srinivas Mishra, Alpha Sarita Barik, 2015 .

Hardware Implementation of Mix Column Step in AES

Manoranjan Pradhan, Subba Rao Polamuri, Pratap Kumar Dakua, 2012 .

An efficient redundant binary adder with revised computational rules

Manoranjan Pradhan, Ranjan Kumar Barik, Bandan Kumar Bhoi, 2018, Comput. Electr. Eng..

Intrusion Prevention System

Sateesh Kumar Pradhan, Manoranjan Pradhan, Bijaya Kumar Panda, 2020, Securing the Internet of Things.

MAC Implementation using Vedic Multiplication Algorithm

Rutuparna Panda, Sushanta Kumar Sahu, Manoranjan Pradhan, 2011 .

Mixture of Decimal and Binary Arithmetic Units For FPGA Based Architecture

Manoranjan Pradhan, Satya Ranjan Sahu, 2020, 2020 4th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech).

Synthesis and simulation study of non-restoring cell architecture layout in perpendicular nano-magnetic logic

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2020 .

Intrusion Detection System (IDS) and Their Types

Sateesh Kumar Pradhan, Manoranjan Pradhan, Chinmaya Kumar Nayak, 2016 .

Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier

Manoranjan Pradhan, Sudhanshu Mishra, 2012 .

A novel vedic divider based crypto-hardware for nanocomputing paradigm: An extended perspective

Neeraj Kumar Misra, Manoranjan Pradhan, Bandan Kumar Bhoi, 2018 .

Energy-Hole Minimization in WSN Using Active Bonding and Separating Coverage

Manoranjan Pradhan, Chinmaya Kumar Nayak, Satyabrata Das, 2016 .

Improved Redundant Binary Adder Realization in FPGA

Manoranjan Pradhan, Satya Ranjan Sahu, Bandan Kumar Bhoi, 2021, Journal of Circuits, Systems and Computers.

Efficient hardware realization of signed arithmetic operation using IEN

Manoranjan Pradhan, Ranjan Kumar Barik, Itishree Samal, 2015, 2015 IEEE Power, Communication and Information Technology Conference (PCITC).

Area-Time Efficient Square Architecture

Manoranjan Pradhan, Ranjan Kumar Barik, 2015 .

Time efficient signed Vedic multiplier using redundant binary representation

Rutuparna Panda, Manoranjan Pradhan, Ranjan Kumar Barik, 2017 .