J.C.S. Woo

Analog device design for low power mixed mode applications in deep submicron CMOS technology

H.V. Deshpande, Baohong Cheng, J.C.S. Woo, 2001, IEEE Electron Device Letters.

AC floating-body effects in submicron fully depleted (FD) SOI nMOSFETs and the impact on analog applications

J.C.S. Woo, Ying-Che Tseng, W.M. Huang, 1998, IEEE Electron Device Letters.

Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications

J.C.S. Woo, M. Garg, S.S. Suryagandh, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

J.C.S. Woo, R. Jhaveri, V. Nagavarapu, 2008, IEEE Transactions on Electron Devices.

Device design methodology to optimize low-frequency noise in advanced SOI CMOS technology for RF ICs

J.C.S. Woo, Ying-Che Tseng, W.M. Huang, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Novel Device structures for Sub-25nm Generation

Jun Yuan, J.C.S. Woo, R. Jhaveri, 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling

J.C.S. Woo, Seong-Dong Kim, H. Wada, 2004, IEEE Transactions on Semiconductor Manufacturing.

Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS

A. Inani, J.C.S. Woo, Baohong Cheng, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).