Hirobumi Watanabe

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

K. Taniguchi, K. Taniguchi, H. Watanabe, 2003 .

Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

Hirobumi Watanabe, N. Ueda, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Grain Boundary Properties of Boron-Doped Polycrystalline Si1-XGeX Resistors with Small Process Fluctuation and Small Drift for High Precision Analog ICs

K. Taniguchi, Hirobumi Watanabe, M. Dainin, 2003 .