K. Maitra

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

S. Samavedam, X. Yang, K. Maitra, 2011, IEEE 2011 International SOI Conference.

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

P. Oldiges, K. Maitra, V. Narayanan, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Charge trapping in aggressively scaled metal gate/high-k stacks

K. Maitra, V. Narayanan, R. Carruthers, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

K. Maitra, V. Narayanan, R. Carruthers, 2006, IEEE Electron Device Letters.