Feipei Lai

A bipartition-codec architecture to reduce power in pipelined circuits

Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero

Feipei Lai, Yen-Jen Chang, Chia-Lin Yang, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamic zero-sensitivity scheme for low-power cache memories

Feipei Lai, Yen-Jen Chang, 2005, IEEE Micro.