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A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation

B.J. Park, D. Shum, J. Liu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 0.168/spl mu/m/sup 2//0.11/spl mu/m/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

T. Kirihata, S.S. Iyer, J. Liu, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..