Murat Askar

发表

Two fast RSA implementations using high-radix montgomery algorithm

Soner Yesil, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Planar Spiral Inductor Modeling for RFIC Design

Ali Telli, Simsek Demir, Murat Askar, 2003, VLSI.

Motor current signature analysis via four-channel FIR filter banks

Michael J. Devaney, Levent Eren, Murat Askar, 2016 .

Fast constraint graph generation algorithms for VLSI layout compaction

Murat Askar, I. H. Torunoglu, 1994, Proceedings of MELECON '94. Mediterranean Electrotechnical Conference.

Incremental design of high complexity FIR filters by genetic algorithms

Murat Askar, M. Oner, 1999, ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications (IEEE Cat. No.99EX359).

Recursive Algorithms for Bayes Smoothing with Uncertain Observations

Haluk Derin, Murat Askar, 1983, 1983 American Control Conference.

A high speed FPGA implementation of the Rijndael algorithm

A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

A 5 GHz 8×8-Bit Multiplier Using Wave Component Sampling Method

Murat Askar, Refik Sever, M. Askar, 2013 .

Practical performance of planar spiral inductors

Ali Telli, Simsek Demir, Murat Askar, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic

A. Neslin Ismailoglu, Murat Askar, M. Askar, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation

A. Neslin Ismailoglu, Murat Askar, M. Askar, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

A high speed ASIC implementation of the Rijndael algorithm

A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Trellis coded quantization for data hiding

Ersin Esen, Murat Askar, A. Aydin Alatan, 2003, The IEEE Region 8 EUROCON 2003. Computer as a Tool..

Modification of a radio link system from analog to digital

Y. Tanik, Murat Askar, A. Atalar, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Real-Time Motor Fault Detection by 1-D Convolutional Neural Networks

Moncef Gabbouj, Serkan Kiranyaz, Turker Ince, 2016, IEEE Transactions on Industrial Electronics.

A new wave-pipelining methodology: wave component sampling method

Murat Askar, Refik Sever, 2014 .

Heat leakage detection and surveiallance using aerial thermography drone

Murat Askar, Raheleh Eslampanah, Hakan Kayan, 2018, 2018 26th Signal Processing and Communications Applications Conference (SIU).

A high speed FPGA implementation of the Rijndael algorithm

Murat Askar, Refik Sever, B. Okcan, 2004 .

Turkish small satellite program: Goals and policies

Ozan Tekinalp, Murat Askar, 2000 .

Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders

A. Neslin Ismailoglu, Murat Askar, M. Askar, 2007, 2007 IEEE International Symposium on Circuits and Systems.

CMOS LNA design for LEO space S-band applications

Ali Telli, Murat Askar, A. Telli, 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

8×8-Bit multiplier designed with a new wave-pipelining scheme

Murat Askar, Refik Sever, M. Askar, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders

A. Neslin Ismailoglu, Murat Askar, M. Askar, 2008 .

Optimal sequential smoothing with uncertain observations

Haluk Derin, Murat Askar, H. Derin, 1985 .