Michalis D. Galanis

发表

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPGA '04.

Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2006 .

A method for partitioning applications in hybrid reconfigurable architectures

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, Des. Autom. Embed. Syst..

64-bit Block ciphers: hardware implementations and comparison analysis

Michalis D. Galanis, Odysseas G. Koufopavlou, Paris Kitsos, 2004, Comput. Electr. Eng..

Novel Hardware Implementation of the Cipher Message Authentication Code

Michalis D. Galanis, Constantinos E. Goutis, Harris E. Michail, 2008, J. Comput. Networks Commun..

Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, The Journal of Supercomputing.

Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, PATMOS.

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPL.

A partitioning flow for accelerating applications in processor-FPGA systems

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2005 .

Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, GLSVLSI '07.

Performance Improvements of DSP Applications on a Generic Reconfigurable Platform

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2007 .

A partitioning methodology for accelerating applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, Design, Automation and Test in Europe.

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

Optimized hardware implementation for tile-based convolutional 2-D discrete wavelet transform

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2006 .

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2004, SCOPES.

Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, PATMOS.

Architectures and Hardware Implementations of the 64-bit MISTY1 Block Cipher

Michalis D. Galanis, Paris Kitsos, Odysseas Koufopavlou, 2004, IACR Cryptol. ePrint Arch..

Partitioning DSP applications to different granularity reconfigurable hardware

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems

Michalis D. Galanis, Constantinos E. Goutis, Athanasios Kakarountas, 2006, Microelectron. J..

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, The Journal of Supercomputing.

A high performance data-path to accelerate DSP kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, The Journal of Supercomputing.

A Novel Data-Path for Accelerating DSP Kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, SAMOS.

A Framework for Data Partitioning for C++ Data-Intensive Applications

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2004, Des. Autom. Embed. Syst..

Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, The Journal of Supercomputing.

Accelerating applications by mapping critical kernels on coarse-grain reconfigurable hardware in hybrid systems

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

Comparison of the Hardware Implementation of Stream Ciphers

Michalis D. Galanis, Constantinos E. Goutis, Paris Kitsos, 2005, Int. Arab J. Inf. Technol..

A high-performance data path for synthesizing DSP kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, PATMOS.

High-speed hardware implementations of the KASUMI block cipher

Michalis D. Galanis, Odysseas G. Koufopavlou, Paris Kitsos, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3)

Michalis D. Galanis, Odysseas G. Koufopavlou, Paris Kitsos, 2005, J. Circuits Syst. Comput..

Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path

Michalis D. Galanis, Constantinos E. Goutis, 2008, J. Syst. Archit..

Compiler assisted architectural exploration for coarse grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, GLSVLSI '07.

A unified evaluation framework for coarse grained reconfigurable array architectures

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, CF '07.

Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher

Michalis D. Galanis, Odysseas G. Koufopavlou, Paris Kitsos, 2006, J. Circuits Syst. Comput..

Exploiting the distributed foreground memory in coarse grain reconfigurable arrays for reducing the memory bottleneck in DSP applications

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2005 .

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2009, The Journal of Supercomputing.

Speedups from executing critical software segments to coarse-grain reconfigurable logic

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2006 .

A methodology for partitioning DSP applications in hybrid reconfigurable systems

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Resource aware mapping on coarse grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2009, Microprocess. Microsystems.

Resource constrained modulo scheduling for coarse-grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Partitioning signal processing applications to different granularity reconfigurable logic

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2005 .

A framework for partitioning computational intensive applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Optimized mapping for enchancing the operation parallelism in coarse-grained reconfigurable arrays

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis, 2006 .

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, Integr..

A compiler method for memory-conscious mapping of applications on coarse-grained reconfigurable architectures

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Speedups in embedded systems with a high-performance coprocessor datapath

Spyros Tragoudas, Michalis D. Galanis, Constantinos E. Goutis, 2007, TODE.

Performance Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Accelerating DSP applications on a mixed granularity platform with a new reconfigurable coarse-grain data-path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2005, J. Circuits Syst. Comput..

Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher

Michalis D. Galanis, Odysseas G. Koufopavlou, Paris Kitsos, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Comparison of the hardware architectures and FPGA implementations of stream ciphers

Michalis D. Galanis, Constantinos E. Goutis, Odysseas G. Koufopavlou, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Performance improvements using coarse-grain reconfigurable logic in embedded SOCs

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2007, Microprocess. Microsystems.

Power aware data type refinement on the HIPERLAN/2

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.