George Theodoridis

发表

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPGA '04.

An efficient reconfigurable multiplier architecture for Galois field GF(2m)

George Theodoridis, Odysseas G. Koufopavlou, Paris Kitsos, 2003, Microelectron. J..

Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs

George Athanasiou, Thanos Stouraitis, George Theodoridis, 2016, J. Circuits Syst. Comput..

A method for partitioning applications in hybrid reconfigurable architectures

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, Des. Autom. Embed. Syst..

Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers

Dimitrios Soudris, George Theodoridis, Athanasios Kakarountas, 2006, J. Low Power Electron..

Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers

Dimitrios Soudris, George Theodoridis, Constantinos E. Goutis, 2000, PATMOS.

FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links

George-Othon Glentis, Kristina Georgoulakis, George Theodoridis, 2015, 2015 23rd European Signal Processing Conference (EUSIPCO).

An reconfigurable multiplier in GF(2/sup m/) for elliptic curve cryptosystem

George Theodoridis, Odysseas G. Koufopavlou, Paris Kitsos, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

An integer linear programming model for mapping applications on hybrid systems

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2009, IET Comput. Digit. Tech..

A performance enhancement approach based on tweak process scheduling for a P1619 core

George Theodoridis, Athanasios Kakarountas, Thanasis Tsakoulis, 2016, 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2006, ARC.

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPL.

A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter

George Theodoridis, Nikolaos Kefalas, 2015, 2015 IEEE 5th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications

George Theodoridis, Constantinos E. Goutis, Athanasios Kakarountas, 2006, The Journal of Supercomputing.

A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools

George Theodoridis, Dimitrios Soudris, S. Vassiliadis, 2007 .

A hardware implementation of the JVT Rate Control for H.264

George Theodoridis, Nikolaos Kefalas, 2014, 2014 22nd Telecommunications Forum Telfor (TELFOR).

A fast and accurate delay dependent method for switching estimation of large combinational circuits

Dimitrios Soudris, George Theodoridis, Constantinos E. Goutis, 2002, J. Syst. Archit..

A Novel Constant-Time Fault-Secure Binary Counter

George Theodoridis, Constantinos E. Goutis, Athanasios Kakarountas, 2004, PATMOS.

A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures

George Theodoridis, Nikos S. Voros, Panayiotis Alefragis, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter

George Theodoridis, Nikolaos Kefalas, G. Theodoridis, 2015, Integr..

The ARISE Reconfigurable Instruction Set Extensions Framework

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

A hybrid approach for mapping and scheduling on heterogeneous multicore systems

George Theodoridis, Nikos S. Voros, Panayiotis Alefragis, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

Task graph mapping and scheduling on heterogeneous architectures under communication constraints

George Theodoridis, Nikos S. Voros, Panayiotis Alefragis, 2017, 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

A partitioning methodology for accelerating applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, Design, Automation and Test in Europe.

Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach

Umut Durak, Jürgen Becker, George Theodoridis, 2018, ARC.

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2004, SCOPES.

A high performance data-path to accelerate DSP kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

High-Speed FPGAImplementation oftheSHA-1HashFunction

George Theodoridis, Th. Laopoulos, Athanasios Kakarountas, 2005 .

Cost-effective optical transponders for deployed metropolitan area networks

George-Othon Glentis, Kristina Georgoulakis, George Theodoridis, 2016 .

On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2012, SECRYPT.

Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions

George Theodoridis, Constantinos E. Goutis, Nikolaos D. Zervas, 2000, PATMOS.

Optimising the SHA-512 cryptographic hash function on FPGAs

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, IET Comput. Digit. Tech..

A Novel Data-Path for Accelerating DSP Kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, SAMOS.

Logic Level Power Estimation

George Theodoridis, Costas E. Goutis, 2002 .

A Framework for Data Partitioning for C++ Data-Intensive Applications

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2004, Des. Autom. Embed. Syst..

High-performance FPGA implementations of the cryptographic hash function JH

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, IET Comput. Digit. Tech..

High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2012, SECRYPT.

An automated development framework for a RISC processor with reconfigurable instruction set extensions

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

A high throughput pipelined architecture for H.264/AVC deblocking filter

George Theodoridis, Nikolaos Kefalas, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Logic Level Power Optimization

Dimitrios Soudris, George Theodoridis, 2002 .

A high-performance data path for synthesizing DSP kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A novel high-speed counter with counting rate independent of the counter's length

George Theodoridis, Constantinos E. Goutis, Athanasios Kakarountas, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2014, Integr..

Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming

George Theodoridis, Nikos S. Voros, Panayiotis Alefragis, 2017, TODE.

FPGA Implementations for Volterra DFEs

George Theodoridis, Andreas Emeretlis, 2014, Panhellenic Conference on Informatics.

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, PATMOS.

A high-speed and area efficient hardware implementation of AES-128 encryption standard

George Theodoridis, Constantinos E. Goutis, H. E. Michail, 2005 .

A methodology for partitioning DSP applications in hybrid reconfigurable systems

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, 2005 IEEE International Symposium on Circuits and Systems.

ARISE Machines: Extending Processors with Hybrid Accelerators

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2008, ARC.

Throughput/Area Trade-Offs of Loop-Unrolling, Functional and Structural Pipeline for Skein Hash Function

George Athanasiou, George Theodoridis, Harris E. Michail, 2013 .

Behavioral-level event-driven power management for DECT digital receivers

Dimitrios Soudris, George Theodoridis, Nikolaos D. Zervas, 2005, Microelectron. J..

High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard

George Theodoridis, Nikolaos Kefalas, G. Theodoridis, 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, J. Circuits Syst. Comput..

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2016, Microprocess. Microsystems.

A framework for partitioning computational intensive applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms

George Theodoridis, Nikos S. Voros, Panayiotis Alefragis, 2016, TECS.

Exploring opportunities to improve the performance of a reconfigurable instruction set processor

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2007 .

An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC

George Theodoridis, Nikolaos Kefalas, 2014, 2014 6th International Symposium on Communications, Control and Signal Processing (ISCCSP).

A RISC architecture extended by an efficient tightly coupled reconfigurable unit

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2006 .

An efficient probabilistic method for logic circuits using real delay gate model

Thanos Stouraitis, Dimitrios Soudris, George Theodoridis, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

An Application Development Framework for ARISE Reconfigurable Processors

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2009, TRETS.

Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard

George Theodoridis, N. Kefalas, 2019, Integr..

Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion

George Theodoridis, Nikos S. Voros, Panayiotis Alefragis, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Accelerating DSP applications on a mixed granularity platform with a new reconfigurable coarse-grain data-path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2005, J. Circuits Syst. Comput..

High speed binary counter based on 1D Cellular Automata

George Theodoridis, Athanasios Kakarountas, Christoforos Christakis, 2016, 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST).

A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard

George Theodoridis, Nikolaos Kefalas, 2018, 2018 41st International Conference on Telecommunications and Signal Processing (TSP).

The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators

George Theodoridis, Spiridon Nikolaidis, Nikolaos Vassiliadis, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low power design of a multi-mode transceiver

Dimitrios Soudris, George Theodoridis, Constantinos E. Goutis, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2007, Microprocess. Microsystems.

Power aware data type refinement on the HIPERLAN/2

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

Switching activity estimation under real-gate delay using timed Boolean functions

Dimitrios Soudris, George Theodoridis, Constantinos E. Goutis, 2000 .