R. Jha

A capacitance-based methodology for work function extraction of metals on high-/spl kappa/

Y.H. Kim, V. Misra, R. Choi, 2004, IEEE Electron Device Letters.

Evaluation of Fermi level pinning in low, midgap and high workfunction metal gate electrodes on ALD and MOCVD HfO/sub 2/ under high temperature exposure

Jae Hoon Lee, B. Chen, V. Misra, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

E. Luckowski, H. Bu, V. Narayanan, 2008, 2008 IEEE International Electron Devices Meeting.

Work Function Tuning Via Interface Dipole by Ultrathin Reaction Layers Using AlTa and AlTaN Alloys

V. Misra, V. Misra, R. Jha, 2006, IEEE Electron Device Letters.

Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS

V. Misra, Jae-Hoon Lee, V. Misra, 2003, IEEE International Electron Devices Meeting 2003.