Aloke Saha

发表

Systematic design strategy for DPL-based ternary logic circuit

Aloke Saha, Narendra Deo Singh, 2020 .

Novel CMOS multi-bit counter for speed-power optimization in multiplier design

Dipankar Pal, Aloke Saha, Rahul Pal, 2018 .

Low-power 6-GHz wave-pipelined 8b x 8b multiplier

Mahesh Chandra, Dipankar Pal, Aloke Saha, 2013, IET Circuits Devices Syst..

Novel Approach to Design DPL-based Ternary Logic Circuits

Rakesh Kumar Singh, Aloke Saha, Rahul Raj, 2018, 2018 IEEE Electron Devices Kolkata Conference (EDKCON).

Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier

Dipankar Pal, Aloke Saha, Mahesh Chandra, 2017 .

Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication

Jayanta Ghosh, Aloke Saha, Rahul Pal, 2020 .

Study on LP-HS logic for high performance digital applications

Mrinmoy Chakraborty, Aloke Saha, 2017, 2017 Devices for Integrated Circuit (DevIC).

LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

Sushil Kumar, Mrinmoy Chakraborty, Aloke Saha, 2017 .

DPL-based novel CMOS 1-Trit Ternary Full-Adder

Dipankar Pal, Rakesh Kumar Singh, Pragya Gupta, 2020 .

DPL-based novel Binary-to-ternary converter on CMOS technology

Dipankar Pal, Aloke Saha, 2018 .

Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology

Aloke Saha, Marisha Gautam, Pratik Rajhans, 2020, 2020 National Conference on Emerging Trends on Sustainable Technology and Engineering Applications (NCETSTEA).

DPL-Based Novel 1-Trit Ternary Half-Subtractor

Aloke Saha, Narendra Deo Singh, Rahul Raj, 2020 .

Efficient ternary comparator on CMOS technology

Dipankar Pal, Aloke Saha, Narendra Deo Singh, 2021, Microelectron. J..

Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier

Dipankar Pal, Aloke Saha, Rakesh Kumar Singh, 2022, Microelectron. J..