Yasuhiro Konishi

Development of Electric 4WD System For Compact Hybrid Car

Kantaro Yoshimoto, Yasuhiro Konishi, Masahito Taira, 2019 .

Semiconductor memory device with a split leseverstaerker and process operation for their

Yoshinori Inoue, Masaki Kumanoya, Yasuhiro Konishi, 1989 .

FPM 14.3: A 38ns 4Mb DRAM with a Battery Back·up (BBU) Mode

Yoichi Tobita, Masaki Kumanoya, Tsutomu Yoshihara, 1990 .

The synchronous semiconductor memory device having a plurality of banks

Yasuhiro Konishi, Takahiko Fukiage, Mikio Sakurai, 1997 .

A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

Akira Yamazaki, Masaki Kumanoya, N. Watanabe, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

A 34-ns 16-Mb DRAM with controllable voltage down-converter

Hideto Hidaka, Masaki Tsukude, Kazuyasu Fujishima, 1992 .

A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme (Special Section on High Speed and High Density Multi Functional LSI Memories)

Akira Yamazaki, Naoya Watanabe, Masaki Kumanoya, 1994 .

Influence of Powder Wettability on Production Yield of Composite Particles in a Horizontal Mixer

Yasuhiro Konishi, Shogo Nakano, Toshiyuki Nomura, 2014 .

A semiconductor memory device having a plurality of banks

Yasuhiro Konishi, Takahiko Fukiage, Mikio Sakurai, 1997 .