Debjit Sinha

发表

TAU 2013 variation aware timing analysis contest

Jia Wang, Ahmed Shebaita, Luís Guerra e Silva, 2013, ISPD '13.

Timing analysis with nonseparable statistical and deterministic variations

Jinjun Xiong, Vladimir Zolotov, Jeffrey G. Hemmett, 2012, DAC Design Automation Conference 2012.

Advances in computation of the maximum of a set of random variables

Hai Zhou, Narendra V. Shenoy, Debjit Sinha, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Optimal gate sizing for coupling-noise reduction

Hai Zhou, Chris C. N. Chu, Debjit Sinha, 2004, ISPD '04.

Statistical Timing Analysis considering Multiple-Input Switching

Debjit Sinha, Vasant Rao, Chaitanya Peddawad, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Generation and use of statistical timing macro-models considering slew and load variability

Jin Hu, Vladimir Zolotov, Debjit Sinha, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Yield driven gate sizing for coupling-noise reduction under uncertainty

Hai Zhou, Debjit Sinha, H. Zhou, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A Hierarchical Transistor and Gate-Level Statistical Timing Flow for Microprocessor Designs

Sachin Gupta, Chandu Visweswariah, Debjit Sinha, 2009 .

Analysis and optimization under crosstalk and variability in deep sub-micron vlsi circuits

Hai Zhou, Debjit Sinha, H. Zhou, 2006 .

Reversible Statistical max/min Operation: Theory and Applications to Timing

Jinjun Xiong, Chandu Visweswariah, Debjit Sinha, 2012 .

An algorithm for trading off quantization error with hardware resources for MATLAB-based FPGA design

Sanghamitra Roy, Prithviraj Banerjee, Debjit Sinha, 2005, IEEE Transactions on Computers.

TAU 2014 contest on removing common path pessimism during timing analysis

Jin Hu, Debjit Sinha, Igor Keller, 2014, ICCAD.

A distributed timing analysis framework for large designs

Martin D. F. Wong, Tsung-Wei Huang, Natesan Venkateswaran, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

Hai Zhou, Debjit Sinha, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Statistical path tracing in timing graphs

Debjit Sinha, Nitin Srimal, Vasant Rao, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment

Hai Zhou, Prithviraj Banerjee, Debjit Sinha, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Practical statistical static timing analysis with current source models

Vladimir Zolotov, Debjit Sinha, Michael H. Wood, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Statistical Timing Yield Optimization by Gate Sizing

Hai Zhou, Narendra V. Shenoy, Debjit Sinha, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Statistical gate sizing for timing yield optimization

Hai Zhou, Narendra V. Shenoy, Debjit Sinha, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

Debjit Sinha, Hai Zhou, 2004, ICCAD 2004.

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment

Hai Zhou, Prithviraj Banerjee, Debjit Sinha, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A timing dependent power estimation framework considering coupling

Hai Zhou, Yehea I. Ismail, DiaaEldin Khalil, 2006, ICCAD.

Gate-size optimization under timing constraints for coupling-noise reduction

Hai Zhou, Debjit Sinha, H. Zhou, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reversible statistical max/min operation: Concept and applications to timing

Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, 2012, DAC Design Automation Conference 2012.

Table of Contents: MICRO-39 2006 39 th Annual International Symposium on Microarchitecture

Hai Zhou, Wei Liu, Shan Lu, 2006 .

Statistical Timing Analysis With Coupling

Hai Zhou, Debjit Sinha, H. Zhou, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TAU 2014 contest on removing common path pessimism during timing analysis: Special session paper: Common path pessimism removal (CPPR)

Jin Hu, Debjit Sinha, Igor Keller, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A unified framework for statistical timing analysis with coupling and multiple input switching

Hai Zhou, Debjit Sinha, H. Zhou, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Yield-Aware Cache Architectures

Hai Zhou, Jonathan Adams, Gokhan Memik, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise

Soroush Abbaspour, Chandu Visweswariah, Debjit Sinha, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects

Hai Zhou, Narendra V. Shenoy, Jianfeng Luo, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Constrained aggressor et selection for maximum coupling noise

Soroush Abbaspour, Debjit Sinha, Alex Rubin, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Driver waveform computation for timing analysis with multiple voltage threshold driver models

Soroush Abbaspour, Peter Feldmann, Debjit Sinha, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Advances in Computation of the Maximum of a Set of Gaussian Random Variables

Hai Zhou, Narendra V. Shenoy, Debjit Sinha, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains

Vladimir Zolotov, Natesan Venkateswaran, Debjit Sinha, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Speeding up computation of the max/min of a set of Gaussians for statistical timing analysis and optimization

Nitin Chandrachoodan, Chandu Visweswariah, Debjit Sinha, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

Debjit Sinha, Adil Bhanji, Chaobo Li, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Constrained aggressor set selection for maximum coupling noise

Soroush Abbaspour, Debjit Sinha, Alex Rubin, 2008, ICCAD 2008.