Toshiaki Iwamatsu

发表

A Robust Silicon-on-Insulator Static-Random-Access-Memory Architecture by using Advanced Actively Body-Bias Controlled Technology

Koji Nii, Y. Inoue, Hirofumi Shinohara, 2008 .

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control

Cong-Kha Pham, Nobuyuki Sugii, Koichiro Ishibashi, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Y. Ohji, M. Inuishi, Yuuichi Hirano, 2004 .

Delayed-ABC SOI for crosstalk noise repair

Akira Tada, Masahiro Numa, Masayuki Terai, 2008, IEICE Electron. Express.

Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect

Jun Takahashi, Toshiaki Iwamatsu, Tadashi Nishimura, 1995 .

A 0.05×0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory

Akira Sato, Yukio Maki, Toshiaki Iwamatsu, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide

K. Shiga, M. Inuishi, Shigenobu Maeda, 2001 .

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Nobuyuki Sugii, Toshiro Hiramoto, Hidekazu Oda, 2008 .

Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

Shigenobu Maeda, Toshiaki Iwamatsu, Shigeto Maegawa, 2002, Digest. International Electron Devices Meeting,.

Electrical Characteristics and Crystal Quality Analysis of Thin-Body Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

Hidekazu Oda, Toshiaki Iwamatsu, Yasuo Inoue, 2009 .

Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current

Nobuyuki Sugii, Toshiro Hiramoto, Hidekazu Oda, 2009 .

Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs and Bulk MOSFETs

Nobuyuki Sugii, Toshiro Hiramoto, Hideki Makiyama, 2012 .

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Nobuyuki Sugii, Hirofumi Shinohara, Toshiro Hiramoto, 2014 .

Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode

Nobuyuki Sugii, Toshiro Hiramoto, Toshiaki Iwamatsu, 2008 .

Speed enhancement atVdd= 0.4 V and random τpdvariability reduction and analyisis of τpdvariability of silicon on thin buried oxide circuits

Nobuyuki Sugii, Koichiro Ishibashi, Hirofumi Shinohara, 2014 .