A.I. Deckelmann

Optimization of L/sub Gate/ for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

G. Wachutka, A.I. Deckelmann, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

UIS-Failure of DMOS Power Transistors

G. Wachutka, J. Krumrey, F. Hirler, 2002, 32nd European Solid-State Device Research Conference.