Malte Doerper

A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2005, Design, Automation and Test in Europe.

Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips

Rainer Leupers, Heinrich Meyr, Torsten Kempf, 2008, Int. J. Embed. Syst..

A modular simulation framework for architectural exploration of on-chip interconnection networks

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

Early ISS Integration into Network-on-Chip Designs

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2004, SAMOS.

Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2008, SAMOS.

System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

Rainer Leupers, Gerd Ascheid, Heinrich Meyr, 2005 .