H. Umeda

Study of oxide breakdown under very low electric field

K. Shiga, Akinobu Teramoto, K. Azamawari, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Masahide Inuishi, K. Eikyu, Akinobu Teramoto, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Control of nitrogen profile in radical nitridation of SiO2 films.

Tadahiro Ohmi, Shimpei Tsujikawa, Akinobu Teramoto, 2004 .

SiN Gate Dielectric with Oxygen-enriched Interface (OI-SiN) Utilizing Dual-core-SiON Technique for hp65-SoC LOP Application

J. Yugami, K. Shiga, K. Ohnishi, 2006, 2006 International Electron Devices Meeting.

Two concerns about NBTI issue: gate dielectric scaling and increasing gate current

J. Yugami, S. Tsujikawa, H. Umeda, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

A simple approach to optimizing ultra-thin SiON gate dielectrics independently for n- and p-MOSFETs

J. Yugami, K. Shiga, Y. Ohno, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..