Wojciech Maly

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Physical design of the "2.5D" stacked system

Yangdong Deng, Wojciech Maly, Wojciech Maly, 2003, Proceedings 21st International Conference on Computer Design.

Wojciech Maly, Thomas M. Storey, Wojciech Maly, 1990, Proceedings. International Test Conference 1990.

Memory chip for 24-port global register file

Wojciech Maly, M. Patyra, A. Primatic, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

2.5D system integration: a design driven system implementation schema

Yangdong Deng, Wojciech Maly, Wojciech Maly, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

2.5-dimensional VLSI system integration

Yangdong Deng, Wojciech Maly, Wojciech Maly, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design-manufacturing interface. II. Applications [VLSI]

Wojciech Maly, J. Khare, H. T. Heineken, 1998, Proceedings Design, Automation and Test in Europe.

IMPROVING THE QUALITY OF TEST EDUCATION

Wojciech Maly, 1991, 1991, Proceedings. International Test Conference.

Advanced Yield Learning Through Predictive Micro-Yield Modeling

Wojciech Maly, Xiaolei Li, Andrzej J. Strojwas, 1998 .

Can Defect-Tolerant Chips Better Meet the Quality Challenge?

Wojciech Maly, Alex Orailoglu, Michael Nicolaidis, 1996, VTS.

Yield and reliability analysis of digital standard cells with resistive defects

Wojciech Maly, Th. Nirschl, M. Huber, 2000 .

Statistical Simulation of the IC Manufacturing Process

Andrzej J. Strojwas, Wojciech Maly, Wojciech Maly, 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Advanced forecasting of cost and yield

Wojciech Maly, P. K. Nag, H. J. Jacobs, 1998 .

Cost of Silicon Viewed from VLSI Design Perspective

Wojciech Maly, Wojciech Maly, 1994, 31st Design Automation Conference.

VLSI Yield Prediction and Estimation: A Unified Framework

Andrzej J. Strojwas, Wojciech Maly, Stephen W. Director, 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Inductive contamination analysis (ICA) with SRAM application

Wojciech Maly, Jitendra Khare, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Extraction of defect characteristics for yield estimation using the double bridge test structure

M. E. Thomas, Wojciech Maly, J. Khare, 1991, 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers.

Yield modelling and defect tolerance in VLSI : papers presented at the International Workshop on Designing for Yield, Oxford, 1-3 July 1987

Andrzej J. Strojwas, Wojciech Maly, Will Moore, 1988 .

Placement for 2.5-D Integration

Wojciech Maly, Yangdong Steve Deng, 2010 .

Optimal Order of the VLSI IC Testing Sequence

Wojciech Maly, 1986, 23rd ACM/IEEE Design Automation Conference.

Iddq testing for high performance CMOS-the next ten years

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 1996, Proceedings ED&TC European Design and Test Conference.

3-Dimensional VLSI - A 2.5-Dimensional integration Scheme

Wojciech Maly, Yangdong Deng, 2010 .

Test generation for current testing

Wojciech Maly, P. Nigh, Wojciech Maly, 1989, [1989] Proceedings of the 1st European Test Conference.

Abstract 1.0 Introduction

Wojciech Maly, Pranab K. Nag, Jitendra Khare, 2022 .

Tolerance Assignment for IC Selection Tests

Zygmunt Pizlo, Wojciech Maly, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fault tuples in diagnosis of deep-submicron circuits

Wojciech Maly, R. D. Blanton, Rao Desineni, 2002, Proceedings. International Test Conference.

oc" Wafer Release

Wojciech Maly, P. K. Nag, 1995 .

Design-manufacturing interface. I. Vision [VLSI]

Wojciech Maly, J. Khare, H. T. Heineken, 1998, Proceedings Design, Automation and Test in Europe.

Hierarchical extraction of critical area for shorts in very large ICs

Wojciech Maly, Pranab K. Nag, 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

Proximity effect correction for clock-rate maximization

Li Chen, Wojciech Maly, C. Ouyang, 1998, Advanced Lithography.

Estimation of reject ratio in testing of combinatorial circuits

Wojciech Maly, D. M. H. Walker, Jitendra Khare, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Modeling the Economics of Testing: A DFT Perspective

Wojciech Maly, R. D. Blanton, Anne E. Gattiker, 2002, IEEE Des. Test Comput..

Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

Wojciech Maly, J. Khare, D.B.I. Feltham, 1993 .

FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS

Wojciech Maly, Anne Meixner, Wojciech Maly, 1991, 1991, Proceedings. International Test Conference.

Iddq test: sensitivity analysis of scaling

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Chip-scale 3D topography synthesis

Andrzej J. Strojwas, Wojciech Maly, Xiaolei Li, 1998, Advanced Lithography.

Performance-manufacturability tradeoffs in IC design

Wojciech Maly, Hans T. Heineken, 1998, Proceedings Design, Automation and Test in Europe.

What is Design for Manufacturability (DFM)? (Panel Abstract)

Wojciech Maly, Wojciech Maly, 1991, DAC.

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits

Wojciech Maly, Witold A. Pleskacz, Charles H. Ouyang, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Detection of YieEd Trends

Wojciech Maly, H. T. Heineken, Witold A. Pleskacz, 1997 .

A pattern matching algorithm for verification and analysis of very large IC layouts

Andrzej J. Strojwas, Wojciech Maly, Mariusz Niewczas, 1998, ISPD '98.

Circuit design for a large area high-performance crossbar switch

Wojciech Maly, M. Patyra, Wojciech Maly, 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

A Road map of 2.5-D Integration

Wojciech Maly, Yangdong Steve Deng, 2010 .

Simulation of yield/cost learning curves with Y4

Wojciech Maly, P. K. Nag, H. J. Jacobs, 1997 .

Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells

John Paul Shen, Wojciech Maly, F. Joel Ferguson, 1984, ITC.

Prospects for WSI: a manufacturing perspective

Wojciech Maly, 1992, Computer.

A circuit breaker for redundant IC systems

Wojciech Maly, L. R. Carley, 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

2.5-d system integration: a design perspective

Yangdong Deng, Wojciech Maly, 2006 .

Design Case Studies

Wojciech Maly, Yangdong Steve Deng, Wojciech Maly, 2010 .

CMOS BRIIIGING FAULT DETECTION

Wojciech Maly, Thomas M. Storey, Wojciech Maly, 1991 .

Performance assessment of VeSFET-based SRAM

Wojciech Maly, Malgorzata Marek-Sadowska, Ping-Lin Yang, 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Arrangement and method for proof of punktfoermigen errors in integrated circuits.

Wojciech Maly, Michael E. Thomas, Wojciech Maly, 1988 .

Built-in current testing

Wojciech Maly, M. Patyra, 1992 .

Current testing

Wojciech Maly, Wojciech Maly, 1990, Proceedings. International Test Conference 1990.

Proceedings : 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems, Hidden Valley, Pa., November 18-20, 1991

Duncan M. Walker, Wojciech Maly, Wojciech Maly, 1991 .

Yield Estimation and Prediction

Andrzej J. Strojwas, Wojciech Maly, W Stephen, 1990 .

Cost-Oriented Analysis of the 1997 NTRS

Wojciech Maly, 1997 .

Design for testability view on placement and routing

Wojciech Maly, Derek Feltham, Jitendra Khare, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Critical area analysis for design-based yield improvement of VLSI circuits

Wojciech Maly, J. Khare, S. Griep, 1995 .

Computer-aided process monitoring

Wojciech Maly, Samir Bhagwant Naik, 1994 .

Integrated CAD, CAM and CAT of VLSI Circuits and Systems: The CMU Perspective

Rob A. Rutenbar, John Paul Shen, Andrzej J. Strojwas, 1985 .

Vertical slit transistor based integrated circuits (VeSTICs) paradigm

Wojciech Maly, 2009, ISPD '09.

Cost based tradeoff analysis of standard cell designs

Peng Li, Wojciech Maly, Pranab K. Nag, 2000, SLIP '00.

Extracting Defect Density and Size Distributions from Product ICs

Wojciech Maly, R. D. Blanton, Osei Poku, 2006, IEEE Design & Test of Computers.

Benchmarking diagnosis algorithms with a diverse set of IC deformations

Wojciech Maly, Vyacheslav Rovner, R. D. Blanton, 2004, 2004 International Conferce on Test.

Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing

Wojciech Maly, Samir Naik, Frank Agricola, 1993, IEEE Design & Test of Computers.

Yield Models - Comparative Study

Wojciech Maly, 1990 .

SRAM-based extraction of defect characteristics

Wojciech Maly, J. Khare, S. Griep, 1994, Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures.

Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs

Wojciech Maly, Hans T. Heineken, Wojciech Maly, 1996, Proceedings of International Conference on Computer Aided Design.

Future of testing: Reintegration of design, testing and manufacturing

Wojciech Maly, Wojciech Maly, 1996, Proceedings ED&TC European Design and Test Conference.

Rapid Failure Analysis Using

Wojciech Maly, J. Khare, 1996 .

contamination Analysis (ICA) with SRA

Wojciech Maly, J. Khare, 1995 .

Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs

Wojciech Maly, H. T. Heineken, 1996, ICCAD 1996.

Floorplanning for 2.5-D Integration

Wojciech Maly, Yangdong Steve Deng, Wojciech Maly, 2010 .

Current signatures: application

Wojciech Maly, Anne E. Gattiker, 1997, Proceedings International Test Conference 1997.

Extraction of defect size distributions in an IC layer using test structure data

M. E. Thomas, Wojciech Maly, J. Khare, 1994 .

Current signatures for production testing [CMOS ICs]

Wojciech Maly, Anne Gattiker, P. Nigh, 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

Standard cell interconnect length prediction from structural circuit attributes

Wojciech Maly, H. T. Heineken, 1996, Proceedings of Custom Integrated Circuits Conference.

Detection of an antenna effect in VLSI designs

Wojciech Maly, Sury Maturi, Subhendra Ghosh, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

New and Not-So-New Test Challenges of the Next Decade

Wojciech Maly, 1996, ITC.

Estimation of wafer cost for technology design

Wojciech Maly, A. Kersch, H. Jacobs, 1993, Proceedings of IEEE International Electron Devices Meeting.

Progressive bridge identification

Wojciech Maly, R. D. Blanton, Thomas J. Vogels, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Evaluating yield and testing impact of sub-wavelength lithography

Wojciech Maly, R. D. Blanton, Wing Chiu Tam, 2010, 2010 28th VLSI Test Symposium (VTS).

Optimal Order of the VLSI IC Testing Sequence

Wojciech Maly, 1986, DAC 1986.

Fault characterization of standard cell libraries using inductive contamination analysis (ICA)

Wojciech Maly, Jitendra Khare, Nathan Tiday, 1996, Proceedings of 14th VLSI Test Symposium.

Current signatures: application [to CMOS]

Wojciech Maly, Anne E. Gattiker, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Yield estimation model for VLSI artwork evaluation

Wojciech Maly, J. Deszczka, Wojciech Maly, 1983 .

Design for manufacturability in submicron domain

Wojciech Maly, J. Khare, H. T. Heineken, 1996, ICCAD 1996.

Moore's law and physical design of ICs

Wojciech Maly, Wojciech Maly, 1998, ISPD '98.

Limitations to the size of single-chip electronic neural networks

Wojciech Maly, D.B.I. Feltham, 1991, 1991 Proceedings, International Conference on Wafer Scale Integration.

New yield models for DSM manufacturing

Wojciech Maly, P. Simon, Y. Fei, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Feasibility of Large Area Integrated Circuits

Wojciech Maly, 1989 .

Extraction of critical areas for opens in large VLSI circuits

Wojciech Maly, Witold A. Pleskacz, Charles H. Ouyang, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Yield loss forecasting in the early phases of the VLSI design process

Wojciech Maly, J. Khare, H. T. Heineken, 1996, Proceedings of Custom Integrated Circuits Conference.

Smart-substrate multichip-module systems

Wojciech Maly, Anne E. Gattiker, Derek Feltham, 1994, IEEE Design & Test of Computers.

A feasibility study of 2.5D system integration

Wojciech Maly, Y. Deng, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Interconnect characteristics of 2.5-D system integration scheme

Yangdong Deng, Wojciech Maly, Wojciech Maly, 2001, ISPD '01.

Computer-aided design for VLSI circuit manufacturability

Wojciech Maly, Wojciech Maly, 1990, Proc. IEEE.

Manufacturability analysis environment-MAPEX

Wojciech Maly, H. T. Heineken, Wojciech Maly, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Feasibility study of smart substrate multichip modules

Wojciech Maly, Anne E. Gattiker, 1994, Proceedings., International Test Conference.

Design of ICs applying built-in current testing

Wojciech Maly, Marek J. Patyra, Wojciech Maly, 1992, J. Electron. Test..

CAD at the design-manufacturing interface

Wojciech Maly, Witold A. Pleskacz, Pranab K. Nag, 1997, DAC.

CDF Mapper Codef

Wojciech Maly, J. Khare, 1996 .

Quality of Design from an IC Manufacturing Perspective

Wojciech Maly, Wojciech Maly, 2001, ISQED.

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

Wojciech Maly, Andrzej Pfitzner, Thomas Fischer, 2009, 2009 IEEE International Conference on IC Design and Technology.

Design Of Manufacturing Strategy With Wafer Cost Estimation

Wojciech Maly, M. E. Thomas, I. A. Saadat, 1994, International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM.

Toward understanding "Iddq-only" fails

Wojciech Maly, Anne E. Gattiker, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Test generation for current testing (CMOS ICs)

Wojciech Maly, Phil Nigh, Wojciech Maly, 1990, IEEE Design & Test of Computers.

From Contamination to Defects, Faults and Yield Loss

Wojciech Maly, J. Khare, Wojciech Maly, 1996 .

An Automatic 2.5-D Layout Design Flow

Wojciech Maly, Yangdong Steve Deng, Wojciech Maly, 2010 .

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring

Wojciech Maly, Janusz Rajski, Jitendra Khare, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Current Signatures for Production Testing

Wojciech Maly, Phil Nigh, Anne Gattiker, 1996 .

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits

Wojciech Maly, Wojciech Maly, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Physically realistic fault models for analog CMOS neural networks

Wojciech Maly, D.B.I. Feltham, Wojciech Maly, 1991 .

Rapid failure analysis using contamination-defect-fault (CDF) simulation

Wojciech Maly, J. Khare, 1995 .

Fabrication based statistical design of monolithic IC's

Andrzej J. Strojwas, Wojciech Maly, W Stephen, 1981 .

Statistical approach to VLSI

Wojciech Maly, Stephen W. Director, S. W. Director, 1994 .

An algorithm for determining repetitive patterns in very large IC layouts

Andrzej J. Strojwas, Wojciech Maly, Mariusz Niewczas, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

IC design in high-cost nanometer-technologies era

Wojciech Maly, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Are there any alternatives to "known good die" ? /spl lsqb/MCMs/spl rsqb/

Wojciech Maly, Anne Gattiker, M. E. Thomas, 1994, Proceedings of IEEE Multi-Chip Module Conference (MCMC-94).

Layout-driven test generation

Wojciech Maly, Phil Nigh, Wojciech Maly, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Analysis of the impact of proximity correction algorithms on circuit performance

Wojciech Maly, Li Chen, C. Ouyang, 1999 .

A self-testing ALU using built-in current sensing

Wojciech Maly, P. Nigh, Wojciech Maly, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

Failure Analysis of High

Wojciech Maly, Frank Agricola, Wojciech Maly, 1993 .

Modeling the difficulty of sequential automatic test pattern generation

Wojciech Maly, Thomas E. Marchok, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Parametric Yield Maximization

Wojciech Maly, Andrzej J. Strojwas, W Stephen, 1990 .

Extraction of Defect Density and Size Distributions from Wafer Sort Test Results

Wojciech Maly, R. D. Blanton, Thomas Zanon, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Deformations of ic structure in test and yield learning

Wojciech Maly, Thomas M. Storey, R. D. Blanton, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Current signatures [VLSI circuit testing]

Wojciech Maly, Anne E. Gattiker, A. Gattiker, 1996, Proceedings of 14th VLSI Test Symposium.

Yield-oriented computer-aided defect diagnosis

Wojciech Maly, J. Khare, S. Griep, 1995 .

Design for manufacturability in submicron domain

Wojciech Maly, Pranab K. Nag, Jitendra Khare, 1996, Proceedings of International Conference on Computer Aided Design.

Current signatures for integrated circuit test strategy advisor

Wojciech Maly, Anne Gattiker, 1998 .

Computer-aided failure analysis of VLSI circuits using I/sub DDQ/ testing

Wojciech Maly, Samir B. Naik, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Enabling embedded memory diagnosis via test response compression

Wojciech Maly, Janusz Rajski, Jitendra Khare, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Design methodology for defect tolerant integrated circuits

Wojciech Maly, Wojciech Maly, 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

Current sensing for built-in testing of CMOS circuits

Wojciech Maly, P. J. Nigh, L. R. Carley, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

Realistic Fault Modeling for VLSI Testing

Wojciech Maly, Wojciech Maly, 1987, 24th ACM/IEEE Design Automation Conference.

So what is an optimal test mix? A discussion of the SEMATECH methods experiment

Kenneth M. Butler, Robert C. Aitken, Wojciech Maly, 1997, Proceedings International Test Conference 1997.

More Moore: foolish, feasible, or fundamentally different?

Jan M. Rabaey, Robert C. Aitken, Wojciech Maly, 2008, ICCAD.

Statistical Process Simulation

Andrzej J. Strojwas, Wojciech Maly, W Stephen, 1990 .

Computer-Aided Design for VLSl Circuit Manufacturability

Wojciech Maly, Wojciech Maly, 1990 .

The future of IC design, testing, and manufacturing

Wojciech Maly, 1996, IEEE Des. Test Comput..

A Cost Comparison of VLSI Integration Schemes

Wojciech Maly, Yangdong Steve Deng, 2010 .

Improved yield model for submicron domain

Wojciech Maly, Witold A. Pleskacz, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Detection of yield trends

Wojciech Maly, Witold A. Pleskacz, Hans T. Heineken, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Process monitoring oriented IC testing

Wojciech Maly, Samir B. Naik, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

VLSI Design for Manufacturing: Yield Enhancement

Wojciech Maly, Andrzej J. Strojwas, W Stephen, 1989 .

In-line yield prediction methodologies using patterned wafer inspection information

Andrzej J. Strojwas, Wojciech Maly, R. K. Nurani, 1998 .

Challenges in Testing of Mixed Mode Analog/Digital ICs

Wojciech Maly, Wojciech Maly, 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

Vertical slit transistor based integrated circuits (veSTICs): feasibility study

Wojciech Maly, 2011, ISPD '11.

Application of defect simulation as a tool for more efficient failure analysis

Wojciech Maly, J. Khare, S. Griep, 1994 .

Design-manufacturing interface: Part II - applications

Wojciech Maly, P. Simon, Pranab K. Nag, 1998, DATE.

Smart Substrate MCMs

Wojciech Maly, Anne E. Gattiker, 1997, J. Electron. Test..

CMOS bridging fault detection

Wojciech Maly, Thomas M. Storey, 1990, 1991, Proceedings. International Test Conference.

Fault probability prediction for array based designs

Wojciech Maly, D. M. H. Walker, Dinesh D. Gaitonde, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Circuit design for built-in current testing

Wojciech Maly, M. Patyra, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

3D Chips can be cool: Thermal study of VeSFET-based ICs

Wojciech Maly, Malgorzata Marek-Sadowska, Xiang Qiu, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

A Feasibility Study of 2 . 5 D System Integration Yangdong (

Wojciech Maly, Steven Deng, .

Atlas of Ic Technologies,: An Introduction to Vlsi Processes

Wojciech Maly, Wojciech Maly, 1987 .

N-channel Junction-less Vertical Slit Field-Effect Transistor (VeSFET): Fabrication-based Feasibility Assessment

Guo-Qiang Lo, Wojciech Maly, Andrzej Pfitzner, 2012 .

- 1-Multi-Chip Module Smart Substrate Systems

Wojciech Maly, Anne E. Gattiker, Michael E. Thomas, 1998 .