Peichen Pan

Integrating Logic Synthesis, Technology Mapping, and Retiming

Robert K. Brayton, Alan Mishchenko, Satrajit Chatterjee, 2005 .

Logic and layout optimization for sequential circuits

Peichen Pan, 1995 .

Optimal clock period FPGA technology mapping for sequential circuits

C.L. Liu, Peichen Pan, P. Pan, 1996, 33rd Design Automation Conference Proceedings, 1996.