S. Wakabayashi

发表

AN NFA-BASED PROGRAMMABLE REGULAR EXPRESSION MATCHING ENGINE HIGHLY SUITABLE FOR FPGA IMPLEMENTATION

S. Nagayama, Hiroki Takaguchi, Yoichi Wakaba, 2013 .

A Matching Method for Look-ahead Assertion on Pattern Independent Regular Expression Matching Engine

S. Nagayama, Yoichi Wakaba, S. Wakabayashi, 2012 .

A new performance driven placement method with the Elmore delay model for row based VLSIs

T. Koide, S. Wakabayashi, M. Ono, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

A Graph Bisection Algorithm Based on Subgraph Migration (Special Section on VLSI Design and CAD Algorithms)

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1994 .

Table Reference-Based Acceleration of a Lithography Hotspot Detection Method Based on Approximate String Search

Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi, 2017 .

Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers

Shinobu Nagayama, Shin'ichi Wakabayashi, Yoichi Wakaba, 2010 .

On Common Sequence Problems (Applied Combinatorial Theory and Algorithms)

Tohru Kikuno, Shin'ichi Wakabayashi, Noriyoshi Yoshida, 1981 .

A High-Speed Programmable Network Intrusion Detection System Based on a Multi-Byte Transition NFA

S. Nagayama, Hiroki Takaguchi, S. Wakabayashi, 2016 .

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout

T. Koide, S. Wakabayashi, 1999, Integr..

A three-layer over-the-cell multi-channel routing method for a new cell model

T. Koide, S. Wakabayashi, N. Yoshida, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

A Hardware-Based Genetic Algorithm with Adaptive Selection of Crossover Operators:LSI Implementation and Its Evaluation

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, 1998 .

An FPGA-based text search engine for approximate regular expression matching

Shinobu Nagayama, Shin'ichi Wakabayashi, Yuichiro Utan, 2010, 2010 International Conference on Field-Programmable Technology.

Pin assignment with global routing for VLSI building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A systolic graph partitioning algorithm for VLSI design

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds

Yoko Kamidoi, Shin'ichi Wakabayashi, Shun Kawamoto, 2020, 2020 IEEE 44th Annual Computers, Software, and Applications Conference (COMPSAC).

A RISC processor for high-speed execution of genetic algorithms

Shin'ichi Wakabayashi, Tetsushi Koide, Shinya Koizumi, 2001 .

A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1997, Integr..

A Verifiable Secret Sharing Scheme without Using Multi-Party Computations

Takumi Makino, Yoko Kamidoi, Shin'ichi Wakabayashi, 2020, 2020 IEEE 44th Annual Computers, Software, and Applications Conference (COMPSAC).

On three-way graph partitioning

Shin'ichi Wakabayashi, Noriyoshi Yoshida, Yoko Kamidoi, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing

Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi, 2018, DEXA.

A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, T. Koide, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

A floorplanning method with topological constraint manipulation

Shin'ichi Wakabayashi, Tetsushi Koide, Yoshinori Katsura, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

An optimal channel pin assignment with multiple intervals for building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

A parallel algorithm for k‐way graph partitioning

Shin'ichi Wakabayashi, Jun'ichi Miyao, Noriyoshi Yoshida, 1993 .

An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints

Shin'ichi Wakabayashi, Tetsushi Koide, T. Koide, 2000 .

An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair

T. Koide, S. Wakabayashi, S. Nakaya, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

An ILP-Based Optimal Circuit Mapping Method for PLDs

Shinobu Nagayama, Keisuke Inoue, Shin'ichi Wakabayashi, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

On-the-fly crossover adaptation of genetic algorithms

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 1997 .

Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 2001, Systems and Computers in Japan.

A genetic algorithm for generating a steiner tree with wire sizing and buffer insertion

Shin'ichi Wakabayashi, S. Wakabayashi, Masakazu Ohsako, 2001 .

A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout (Special Section on VLSI Design and CAD Algorithms)

T. Koide, S. Wakabayashi, K. Yamatani, 1994 .

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs

Shin'ichi Wakabayashi, Tetsushi Koide, Mitsuhiro Ono, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Gate array placement based on mincut partitioning with path delay constraints

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Efficient FPGA-based Hardware Algorithms for Approximate String Matching

Shinobu Nagayama, Shin'ichi Wakabayashi, Sadatoshi Mikami, 2008 .

Performance Driven Standard Cell Placement Based on Nonlinear Programming

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1994 .

A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations

Shinobu Nagayama, Shin'ichi Wakabayashi, Yoichi Wakaba, 2011, 2011 14th Euromicro Conference on Digital System Design.

A Divide-and-Conquer Approach to the Minimum k -Way Cut Problem

S. Wakabayashi, N. Yoshida, Y. Kamidoi, 1997, Algorithmica.

A hierarchical standard cell placement method based on a new cluster placement model

S. Wakabayashi, H. Kubota, N. Iwauchi, 2002, Asia-Pacific Conference on Circuits and Systems.

Feature Extraction of Clusters Based on FlexDice

Shin'ichi Wakabayashi, Noriyoshi Yoshida, Tomotake Nakamura, 2005, 21st International Conference on Data Engineering Workshops (ICDEW'05).