Cong Hao

发表

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment

Takeshi Yoshimura, Cong Hao, T. Yoshimura, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

Takeshi Yoshimura, Cong Hao, Jianmo Ni, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing

Yi Zhao, Takeshi Yoshimura, Cong Hao, 2018, 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

A particle swarm optimization and branch and bound based algorithm for economical smart home scheduling

Takeshi Yoshimura, Cong Hao, Yangyizhou Wang, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis

Takeshi Yoshimura, Song Chen, Cong Hao, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Primal-dual method based simultaneous functional unit and register binding

Qian Ai, Takeshi Yoshimura, Nan Wang, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Economical Smart Home Scheduling by Cuckoo Search optimization via Levy Flight

Takeshi Yoshimura, Cong Hao, Yangyizhou Wang, 2018, 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS).

Leakage Power Aware Scheduling in High-Level Synthesis

Takeshi Yoshimura, Haoran Zhang, Song Chen, 2014, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Timing and resource constrained leakage power aware scheduling in high-level synthesis

Nan Liu, Takeshi Yoshimura, Haoran Zhang, 2013, 2013 IEEE 10th International Conference on ASIC.

An efficient algorithm for 3D-IC TSV assignment

Takeshi Yoshimura, Nan Ding, Cong Hao, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Power and resource aware scheduling with multiple voltages

Takeshi Yoshimura, Haoran Zhang, Song Chen, 2013, 2013 IEEE 10th International Conference on ASIC.

Economical smart home scheduling for single and multiple users

Takeshi Yoshimura, Cong Hao, 2016, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS).

Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis

Takeshi Yoshimura, Nan Wang, Cong Hao, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis

Takeshi Yoshimura, Nan Wang, Cong Hao, 2017, IEEE Trans. Very Large Scale Integr. Syst..

Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs

Yao Chen, Jiong He, Deming Chen, 2019, FPGA.

Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip

Takeshi Yoshimura, Cong Hao, Wencan Zhang, 2016, 2016 International SoC Design Conference (ISOCC).

Thermal and Wirelength Optimization With TSV Assignment for 3-D-IC

Takeshi Yoshimura, Yi Zhao, Cong Hao, 2019, IEEE Transactions on Electron Devices.

FPGA/DNN Co-Design: An Efficient Design Methodology for 1oT Intelligence on the Edge

Jinjun Xiong, Yuhong Li, Deming Chen, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

A Unified Scheduling Approach for Power and Resource Optimization With Multiple $V_{\mathrm{ dd}}$ or/and $V_{\mathrm{ th}}$ in High-Level Synthesis

Takeshi Yoshimura, Nan Wang, Cong Hao, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

3D-IC signal TSV assignment for thermal and wirelength optimization

Takeshi Yoshimura, Cong Hao, Yuxin Qian, 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Application of on-line machine learning in optimization algorithms: A case study for local search

Takeshi Yoshimura, Cong Hao, 2017, 2017 9th Computer Science and Electronic Engineering (CEEC).

Thermal-aware floorplanning for NoC-sprinting

Takeshi Yoshimura, Hui Zhu, Cong Hao, 2016, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS).

Port assignment for interconnect reduction in high-level synthesis

Takeshi Yoshimura, Song Chen, Cong Hao, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Workload-Aware Approximate Computing Configuration

Xun Jiao, Dongning Ma, Cong Hao, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning

Yuan Xie, Cong Hao, Nan Wu, 2021, ACM Great Lakes Symposium on VLSI.

Port assignment for multiplexer and interconnection optimization

Takeshi Yoshimura, Min-You Wu, Cong Hao, 2013, Fifth Asia Symposium on Quality Electronic Design (ASQED 2013).