Irith Pomeranz

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Selection of a Fault Model for Fault Diagnosis Based on Unique Responses

Irith Pomeranz, Sudhakar M. Reddy, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Broadside Tests for Transition and Stuck-At Faults

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A DELAYFAULTMODELFORAT-SPEED FAULTSIMULATIONAND TESTGENERATION

Irith Pomeranz, Sudhakar M. Reddy, 2006 .

Multiple fault activation cycle tests for transistor stuck-open faults

Irith Pomeranz, Narendra Devta-Prasanna, Arun Gunda, 2010, 2010 IEEE International Test Conference.

Broad-Brush Compaction for Sequential Test Generation

Irith Pomeranz, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Functional Broadside Tests with Minimum and Maximum Switching Activity

Irith Pomeranz, Sudhakar M. Reddy, 2008, J. Low Power Electron..

Functional Broadside Tests With Incompletely Specified Scan-In States

Irith Pomeranz, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Methods for improving transition delay fault coverage using broadside tests

Irith Pomeranz, Narendra Devta-Prasanna, Arun Gunda, 2005, IEEE International Conference on Test, 2005..

On full reset as a design-for-testability technique

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings Tenth International Conference on VLSI Design.

Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation

Irith Pomeranz, Xiaoming Yu, Enamul Amyeen, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines

Irith Pomeranz, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test pattern generation for path delay faults in synchronous sequential circuits using multiple fast clocks and multiple observation times

Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri, 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

Generation of Broadside Transition Fault Test Sets that Detect Four-Way Bridging Faults

Irith Pomeranz, S. M. Reddy, 2006 .

A convergent procedure for partially-reachable states

Irith Pomeranz, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Generation of test cases for hardware design verification of a super-scalar Fetch Processor

Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

On n-detection test sets and variable n-detection test sets fortransition faults

Irith Pomeranz, Sudhakar M. Reddy, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity

Irith Pomeranz, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A flexible path selection procedure for path delay fault testing

Irith Pomeranz, Sudhakar M. Reddy, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults

Irith Pomeranz, 2020, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

On the Correction of Multiple Design Errors in Combinational Logic Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1993 .

On multiple bridging faults

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 28th VLSI Test Symposium (VTS).

The Multiple Observation Time Test Strategy

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1992, IEEE Trans. Computers.

On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes

Irith Pomeranz, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Vector-based functional fault models for delay faults

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation

Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 14th IEEE European Test Symposium.

Padding of Multicycle Broadside and Skewed-Load Tests

Irith Pomeranz, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault simulation under the multiple observation time approach using backward implications

Irith Pomeranz, Sudhakar M. Reddy, 1997, DAC.

Test data volume reduction by test data realignment

Irith Pomeranz, Sudhakar M. Reddy, 2003, 2003 Test Symposium.

On Error Correction In Macro-based Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Dynamic test compaction for bridging faults

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2005, Sixth international symposium on quality electronic design (isqed'05).

A built-in self-test method for diagnosis of synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, IEEE Trans. Very Large Scale Integr. Syst..

A Metric for Identifying Detectable Path Delay Faults

Irith Pomeranz, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing

Irith Pomeranz, Sudhakar M. Reddy, 1995, IEEE Trans. Computers.

On diagnosis of pattern-dependent delay faults

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceedings 37th Design Automation Conference.

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Irith Pomeranz, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multicycle Broadside and Skewed-Load Tests for Test Compaction

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A method for identifying robust dependent and functionally unsensitizable paths

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1997, Proceedings Tenth International Conference on VLSI Design.

On the feasibility of fault simulation using partial circuit descriptions

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceedings of the Ninth Asian Test Symposium.

On generating pseudo-functional delay fault tests for scan designs

Irith Pomeranz, Sudhakar M. Reddy, Zhuo Zhang, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Path-oriented transition fault test generation considering operating conditions

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2005, European Test Symposium (ETS'05).

A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests

Irith Pomeranz, Li Chen, Srinivas Patil, 2006, 2006 IEEE International Test Conference.

Test Generation for Open Defects in CMOS Circuits

Irith Pomeranz, Sudhakar M. Reddy, Narendra Devta-Prasanna, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Functional broadside tests for embedded logic blocks

Irith Pomeranz, 2012, IET Comput. Digit. Tech..

Test Compaction by Test Removal Under Transparent Scan

Irith Pomeranz, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences

Irith Pomeranz, 2018, ACM Trans. Design Autom. Electr. Syst..

On test data volume reduction for multiple scan chain designs

Irith Pomeranz, Sudhakar M. Reddy, Kohei Miyase, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

On improving a fault simulation based test generator for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2001, Proceedings 10th Asian Test Symposium.

Static test compaction for delay fault test sets consisting of broadside and skewed-load tests

Irith Pomeranz, I. Pomeranz, 2011, 29th VLSI Test Symposium.

On reducing test data volume and test application time for multiple scan chain designs

Irith Pomeranz, Sudhakar M. Reddy, Huaxing Tang, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs

Irith Pomeranz, I. Pomeranz, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Definition and generation of partially-functional broadside tests

Irith Pomeranz, Sudhakar M. Reddy, 2009, IET Comput. Digit. Tech..

A partitioning technique for identification of error-capturing scan cells in scan-BIST

Irith Pomeranz, Sudhakar M. Reddy, Chaowen Yu, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Test generation for path delay faults based on learning

Irith Pomeranz, Sudhakar M. Reddy, 1993, ICCAD.

NEST: a nonenumerative test generation method for path delay faults in combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On fault equivalence, fault dominance, and incompletely specified test sets

Irith Pomeranz, Sudhakar M. Reddy, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1993, 30th ACM/IEEE Design Automation Conference.

On Fault Simulation for Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 1995, IEEE Trans. Computers.

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions

Irith Pomeranz, Sudhakar M. Reddy, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Performance aware partitioning for 3D-SOCs

Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker, 2012, 2012 International SoC Design Conference (ISOCC).

Synthesis of multi-level combinational circuits for complete robust path delay fault testability

Irith Pomeranz, Sudhakar M. Reddy, Niraj K. Jha, 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

A measure of quality for n-detection test sets

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Transactions on Computers.

Implication and evaluation techniques for proving fault equivalence

Irith Pomeranz, Vamsi Boppana, W. Kent Fuchs, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Computing Seeds for LFSR-Based Test Generation From Nontest Cubes

Irith Pomeranz, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On Test Generation by Input Cube Avoidance

Irith Pomeranz, Sudhakar M. Reddy, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Fault dictionary compression and equivalence class computation for sequential circuits

Irith Pomeranz, W. Kent Fuchs, Paul G. Ryan, 1993, ICCAD.

Generation of close-to-functional broadside tests with equal primary input vectors

Irith Pomeranz, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

On test generation for transition faults with minimized peak power dissipation

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2004, Proceedings. 41st Design Automation Conference, 2004..

Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence

Irith Pomeranz, I. Pomeranz, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

LOCSTEP: a logic simulation based test generation procedure

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

TOV: Sequential Test Generation by Ordering of Test Vectors

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test vector omission with minimal sets of simulated faults

Irith Pomeranz, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Classes of difficult-to-diagnose transition fault clusters

Irith Pomeranz, I. Pomeranz, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs

Irith Pomeranz, Sudhakar M. Reddy, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Test generation for synchronous sequential circuits using multiple observation times

Irith Pomeranz, Sudhakar M. Reddy, 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

Primary input cones based on test sequences in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2011, IET Comput. Digit. Tech..

Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm

Irith Pomeranz, Srikanth Venkataraman, Shraddha Bodhe, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Preferred Fill: A Scalable MethodtoReduceCapture PowerforScan BasedDesigns

Irith Pomeranz, Xijiang Lin, S. Remersaro, 2006 .

Defect diagnosis based on pattern-dependent stuck-at faults

Irith Pomeranz, Sudhakar M. Reddy, Enamul Amyeen, 2004, 17th International Conference on VLSI Design. Proceedings..

On Complete Functional Broadside Tests for Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, Hangkyu Lee, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On path selection for delay fault testing considering operating conditions [logic IC testing]

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

Computation of Seeds for LFSR-Based n-Detection Test Generation

Irith Pomeranz, 2017, ACM Trans. Design Autom. Electr. Syst..

Test enrichment for path delay faults using multiple sets of target faults

Irith Pomeranz, S. M. Reddy, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Sharing Logic for Built-In Generationof Functional Broadside Tests

Irith Pomeranz, 2014, IEEE Transactions on Computers.

Diagnosis of transition fault clusters

Irith Pomeranz, I. Pomeranz, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Techniques for improving the efficiency of sequential circuit test generation

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Effectiveness of scan-based delay fault tests in diagnosis of transition faults

Irith Pomeranz, Sudhakar M. Reddy, 2007, IET Comput. Digit. Tech..

ACHIEVING COMPLETE DELAY FAULT TESTABILITY BY EXTRA INPUTS

Irith Pomeranz, Sudhakar M. Reddy, 1991, 1991, Proceedings. International Test Conference.

On compacting test sets by addition and removal of test vectors

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1994, Proceedings of IEEE VLSI Test Symposium.

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Irith Pomeranz, Srikanth Venkataraman, Naixing Wang, 2019, ACM Trans. Design Autom. Electr. Syst..

Constrained test generation for embedded synchronous sequential circuits with serial-input access

Irith Pomeranz, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GALLOP: genetic algorithm based low power FSM synthesis by simultaneous partitioning and state assignment

Irith Pomeranz, Sudhakar M. Reddy, Ganesh Venkataraman, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Don't Care Identification and Statistical Encoding for Test Data Compression

Irith Pomeranz, Sudhakar M. Reddy, Kohei Miyase, 2004, IEICE Trans. Inf. Syst..

An optimal algorithm for cycle breaking in directed graphs

Irith Pomeranz, Zvi Kohavi, Tatiana Orenstein, 1995, J. Electron. Test..

On the detection of reset faults; in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings Tenth International Conference on VLSI Design.

Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences

Irith Pomeranz, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Piecewise-functional broadside tests based on intersections of reachable states

Irith Pomeranz, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

A method to enhance the fault coverage obtained by output response comparison of identical circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-complexity fault diagnosis under the multiple observation time testing approach

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

Synchronization of large sequential circuits by partial reset

Irith Pomeranz, Yuan Lu, I. Pomeranz, 1996, Proceedings of 14th VLSI Test Symposium.

Synthesis for Broadside Testability of Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Topic: T1 Defects, Faults, Variability and Reliability Analysis and Modeling

Irith Pomeranz, Kuen-Jong Lee, Bram Kruseman, 2014 .

Skewed-Load Tests for Transition and Stuck-at Faults

Irith Pomeranz, I. Pomeranz, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GAFPGA: Genetic algorithm for FPGA technology mapping

Irith Pomeranz, Venkataramana Kommu, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

Deterministic broadside test generation for transition path delay faults

Irith Pomeranz, Sudhakar M. Reddy, Bo Yao, 2010, GLSVLSI '10.

Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Combined input test data volume reduction for mixed broadside and skewed-load test sets

Irith Pomeranz, 2016, IET Comput. Digit. Tech..

REDI: an efficient fault oriented procedure to identify redundant faults in combinational logic circuits

Irith Pomeranz, Sudhakar M. Reddy, Chen Wang, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

An improved source design for scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Reducing fault latency in concurrent on-line testing by using checking functions over internal lines

Irith Pomeranz, Sudhakar M. Reddy, 2004 .

A fault simulation based test pattern generator for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

A learning-based method to match a test pattern generator to a circuit-under-test

Irith Pomeranz, Sudhakar M. Reddy, 1993, Proceedings of IEEE International Test Conference - (ITC).

Selection of Functional Test Sequences With Overlaps

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On speeding-up vector restoration based static compaction of test sequences for sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Testing of Fault-Tolerant Hardware Through Partial Control of Inputs

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1993, IEEE Trans. Computers.

On Bias in Transition Coverage of Test Sets for Path Delay Faults

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 19th IEEE Asian Test Symposium.

On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1996, IEEE Trans. Computers.

A bridging fault model for line coverage in the presence of undetected transition faults

Irith Pomeranz, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On test compaction objectives for combinational and sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings Eleventh International Conference on VLSI Design.

Piecewise-Functional Broadside Tests Based on Reachable States

Irith Pomeranz, 2015, IEEE Transactions on Computers.

Test sequences to achieve high defect coverage for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Application of Homing Sequences to Synchronous Sequential Circuit Testing

Irith Pomeranz, Sudhakar M. Reddy, 1994, IEEE Trans. Computers.

Techniques for minimizing power dissipation in scan and combinational circuits during test application

Irith Pomeranz, Sudhakar M. Reddy, Sreejit Chakravarty, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On test data compression and n-detection test sets

Irith Pomeranz, Sudhakar M. Reddy, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A test interface for built-in test of non-isolated scanned cores

Yervant Zorian, Irith Pomeranz, Sudhakar M. Reddy, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects

Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman, 2008, 2008 17th Asian Test Symposium.

On the detection of path delay faults by functional broadside tests

Irith Pomeranz, 2012, 2012 17th IEEE European Test Symposium (ETS).

A postprocessing procedure to reduce the number of different test lengths in a test set for scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings 10th Asian Test Symposium.

On output response compression in the presence of unknown output values

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2002, DAC '02.

Functional test generation for delay faults in combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1995, International Conference on Computer Aided Design.

Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage

Irith Pomeranz, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A DFT approach for path delay faults in interconnected circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2003, 2003 Test Symposium.

Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences

Irith Pomeranz, 2015, IEEE Transactions on Computers.

Output-Dependent Diagnostic Test Generation

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 23rd International Conference on VLSI Design.

Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction

Irith Pomeranz, Srikanth Venkataraman, Shraddha Bodhe, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the characterization and efficient computation of hard-to-detect bridging faults

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests

Irith Pomeranz, 2018, ACM Trans. Design Autom. Electr. Syst..

Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity

Irith Pomeranz, 2011, 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing.

Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity

Irith Pomeranz, Sudhakar M. Reddy, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Static test compaction for mixed broadside and skewed-load transition fault test sets

Irith Pomeranz, 2013, IET Comput. Digit. Tech..

On test data volume reduction for multiple scan chain designs

Irith Pomeranz, Sudhakar M. Reddy, Kohei Miyase, 2003, TODE.

N-pass N-detection Fault Simulation and Its Applications

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the use of fault dominance in n-detection test generation

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Generation of Multi-Cycle Broadside Tests

Irith Pomeranz, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Computers.

Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test-Points

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, 31st Design Automation Conference.

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Use of input necessary assignments for test generation based on merging of test cubes

Irith Pomeranz, 2015, IET Comput. Digit. Tech..

Test data compression based on input-output dependence

Irith Pomeranz, Sudhakar M. Reddy, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Generation of compact multi-cycle diagnostic test sets

Irith Pomeranz, 2013, 2013 18th IEEE European Test Symposium (ETS).

Reducing test application time for full scan circuits by the addition of transfer sequences

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceedings of the Ninth Asian Test Symposium.

Fault diagnosis aware ATE assisted test response compaction

Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration

Irith Pomeranz, Sudhakar M. Reddy, Wu-Tung Cheng, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Low Shift and Capture Power Scan Tests

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Diagnostic Test Generation That Addresses Diagnostic Holes

Irith Pomeranz, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, IEEE Trans. Computers.

Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits

Irith Pomeranz, W. Kent Fuchs, Enamul Amyeen, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Fixed-State Tests for Delay Faults in Scan Designs

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction

Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Application of homing sequences to synchronous sequential circuit testing

Irith Pomeranz, S. M. Reddy, S. Reddy, 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

On improving static test compaction for sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

On Functional Broadside Tests With Functional Propagation Conditions

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Theory and practice of sequential machine testing and testability

Janak H. Patel, Irith Pomeranz, Sudhakar M. Reddy, 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

On reducing test application time for scan circuits using limited scan operations and transfer sequences

Irith Pomeranz, Sudhakar M. Reddy, Yonsang Cho, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults

Irith Pomeranz, Sudhakar M. Reddy, Narendra Devta-Prasanna, 2006, Eleventh IEEE European Test Symposium (ETS'06).

Detection of Internal Stuck-open Faults in Scan Chains

Irith Pomeranz, Sreejit Chakravarty, Narendra Devta-Prasanna, 2008, 2008 IEEE International Test Conference.

Sequence reordering to improve the levels of compaction achievable by static compaction procedures

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation

Irith Pomeranz, Sudhakar M. Reddy, 2011, IET Comput. Digit. Tech..

On multi-cycle test cubes

Irith Pomeranz, 2013, IET Comput. Digit. Tech..

Test Generation for Multiple State-Table Faults in Finite-State Machines

Irith Pomeranz, Sudhakar M. Reddy, 1997, IEEE Trans. Computers.

Z-DFD: design-for-diagnosability based on the concept of Z-detection

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2004 .

At-speed delay testing of synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level

Irith Pomeranz, Sudhakar M. Reddy, Sitaran Yadavalli, 1995, Proceedings of the 8th International Conference on VLSI Design.

Selecting Replacements for Undetectable Path Delay Faults

Irith Pomeranz, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ITEM: an iterative improvement test generation procedure for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, GLSVLSI '01.

On synchronizing sequences and unspecified values in output responses of synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Identifying Biases of a Defect Diagnosis Procedure

Irith Pomeranz, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

The cut delay fault model for guiding the generation of n-detection test sets for transition faults

Irith Pomeranz, Sudhakar M. Reddy, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Transactions on Computers.

Sizes of test sets for path delay faults using strong and weak non-robust tests

Irith Pomeranz, Sudhakar M. Reddy, 2011, IET Comput. Digit. Tech..

On correction of multiple design errors

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis

Irith Pomeranz, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Concurrent online testing of identical circuits using nonidentical input vectors

Irith Pomeranz, Sudhakar M. Reddy, 2005, IEEE Transactions on Dependable and Secure Computing.

On achieving complete coverage of delay faults in full scan circuits using locally available lines

Irith Pomeranz, Sudhakar M. Reddy, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Finding a common fault response for diagnosis during silicon debug

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Gate-level design diagnosis using a learning-based search strategy

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

On pass/fail dictionaries for scan circuits

Irith Pomeranz, 2001, Proceedings 10th Asian Test Symposium.

On undetectable faults in partial scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2002, ICCAD 2002.

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions

Irith Pomeranz, Narendra Devta-Prasanna, Arun Gunda, 2005, 14th Asian Test Symposium (ATS'05).

Diagnostic Fail Data Minimization Using an $N$ -Cover Algorithm

Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences

Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Computers.

Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Design-for-testability for synchronous sequential circuits using locally available lines

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings Design, Automation and Test in Europe.

TEA: A Test Generation Algorithm for Designs with Timing Exceptions

Irith Pomeranz, Wu-Tung Cheng, Xijiang Lin, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

Using Dummy Bridging Faults to Define Reduced Sets of Target Faults

Irith Pomeranz, Sudhakar M. Reddy, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On potential fault detection in sequential circuits

Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1999, DAC '99.

Test vector chains for increasing the fault coverage and numbers of detections

Irith Pomeranz, Sudhakar M. Reddy, 2009, IET Comput. Digit. Tech..

Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length

Irith Pomeranz, 2012, IEEE Transactions on Computers.

Proptest: a property based test pattern generator for sequential circuits using test compaction

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, DAC '99.

Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests

Irith Pomeranz, Sudhakar M. Reddy, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

A comment on "Improving a nonenumerative method to estimate path delay fault coverage"

Irith Pomeranz, Sudhakar M. Reddy, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Vector replacement to improve static-test compaction forsynchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation

Irith Pomeranz, Sudhakar M. Reddy, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks

Irith Pomeranz, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Z-sets and z-detections: circuit characteristics that simplify fault diagnosis

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults

Irith Pomeranz, Sudhakar M. Reddy, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

New Techniques to Reduce the Execution Time of Functional Test Programs

Irith Pomeranz, Giovanni Squillero, Matteo Sonza Reorda, 2017, IEEE Transactions on Computers.

Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence

Irith Pomeranz, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On clustering of undetectable transition faults in standard-scan circuits

Irith Pomeranz, 2011, 29th VLSI Test Symposium.

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

A method to find don't care values in test sequences for sequential circuits

Irith Pomeranz, Yuzo Takamatsu, Yoshinobu Higami, 2003, Proceedings 21st International Conference on Computer Design.

Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution

Irith Pomeranz, Sudhakar M. Reddy, 2009, IET Comput. Digit. Tech..

Testing of scan circuits containing nonisolated random-logic legacycores

Irith Pomeranz, Y. Zonan, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A partitioning and storage based built-in test pattern generation method for scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set

Irith Pomeranz, Sudhakar M. Reddy, 1992, The Fifth International Conference on VLSI Design.

SOC test scheduling using simulated annealing

Irith Pomeranz, Sudhakar M. Reddy, Wei Zou, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Design-for-testability for multi-cycle broadside tests by holding of state variables

Irith Pomeranz, 2014, TODE.

Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests

Irith Pomeranz, 2016, TODE.

On synchronizing sequences and test sequence partitioning

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

On the Switching Activity in Faulty Circuits During Test Application

Irith Pomeranz, Sudhakar M. Reddy, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites

Irith Pomeranz, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Test data compression using don't-care identification and statistical encoding

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion

Irith Pomeranz, Sudhakar M. Reddy, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On determining symmetries in inputs of logic circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, Proceedings of 7th International Conference on VLSI Design.

On static compaction of test sequences for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1996, DAC '96.

Autoscan: a scan design without external scan inputs or outputs

Irith Pomeranz, Sudhakar M. Reddy, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On improving genetic optimization based test generation

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1997, Proceedings European Design and Test Conference. ED & TC 97.

On n-detection test sets and variable n-detection test sets for transition faults

Irith Pomeranz, Sudhakar M. Reddy, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Scan tests with multiple fault activation cycles for delay faults

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2006, 24th IEEE VLSI Test Symposium.

Design-for-testability for path delay faults in large combinational circuits using test points

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Selection of potentially testable path delay faults for test generation

Irith Pomeranz, Sudhakar M. Reddy, Tsutomu Sasao, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

Irith Pomeranz, Sudhakar M. Reddy, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity

Irith Pomeranz, Sudhakar M. Reddy, 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Forward-Looking Reverse Order Fault Simulation for $n$ -Detection Test Sets

Irith Pomeranz, Sudhakar M. Reddy, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On Common-Mode Skewed-Load and Broadside Tests

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Reduced Fault Coverage as a Target for Design Scaffolding Security

Irith Pomeranz, Sandip Kundu, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes

Irith Pomeranz, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Static test compaction for diagnostic test sets of full-scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2010, IET Comput. Digit. Tech..

On the compaction of test sets produced by genetic optimization

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Functional test generation for full scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2000, DATE '00.

Test transformation to improve compaction by statistical encoding

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults

Irith Pomeranz, Xijiang Lin, I. Pomeranz, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

LFSR-Based Generation of Partially-Functional Broadside Tests

Irith Pomeranz, 2016, IEEE Trans. Computers.

Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Transactions on Computers.

Safe Fault Collapsing Based on Dominance Relations

Irith Pomeranz, Sudhakar M. Reddy, 2008, 2008 13th European Test Symposium.

Static test compaction procedure for large pools of multicycle functional broadside tests

Irith Pomeranz, 2018, IET Comput. Digit. Tech..

A novel method of improving transition delay fault coverage using multiple scan enable signals

Irith Pomeranz, Narendra Devta-Prasanna, Arun Gunda, 2005, 2005 International Conference on Computer Design.

Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

Irith Pomeranz, Sudhakar M. Reddy, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Low-power skewed-load tests based on functional broadside tests

Irith Pomeranz, 2014, TODE.

An efficient method to identify untestable path delay faults

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 2001, Proceedings 10th Asian Test Symposium.

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy

Irith Pomeranz, Sudhakar M. Reddy, 2008, 2008 Design, Automation and Test in Europe.

On finding functionally identical and functionally opposite lines in combinational logic circuits

Irith Pomeranz, Sudhakar M. Reddy, 1996, Proceedings of 9th International Conference on VLSI Design.

Test data compression using don't-care identification and statistical encoding [logic testing]

Irith Pomeranz, Sudhakar M. Reddy, Kohei Miyase, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults

Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

STOIC: state assignment based on output/input functions

Irith Pomeranz, Kwang-Ting Cheng, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the coverage of delay faults in scan designs with multiple scan chains

Irith Pomeranz, Sudhakar M. Reddy, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On the effects of test compaction on defect coverage

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 1996, Proceedings of 14th VLSI Test Symposium.

A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set

Irith Pomeranz, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Tuple detection for path delay faults: a method for improving test set quality

Irith Pomeranz, Sudhakar M. Reddy, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Boundary-Functional Broadside and Skewed-Load Tests

Irith Pomeranz, 2019, ACM Trans. Design Autom. Electr. Syst..

Conflict driven techniques for improving deterministic test pattern generation

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

PASTA: partial scan to enhance test compaction

Irith Pomeranz, Sudhakar M. Reddy, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1998, Proceedings Design, Automation and Test in Europe.

Maximal Independent Fault Set for Gate-Exhaustive Faults

Irith Pomeranz, I. Pomeranz, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Z-DFD: design-for-diagnosability based on the concept of Z-detection

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2004, 2004 International Conferce on Test.

ROTCO: a reverse order test compaction technique

Irith Pomeranz, Sudhakar M. Reddy, L. N. Reddy, 1992, Proceedings Euro ASIC '92.

Updating the sets of target faults during test generation for multiple fault models

Irith Pomeranz, 2019, IET Comput. Digit. Tech..

Test compaction for synchronous sequential circuits by test sequence recycling

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults

Irith Pomeranz, 2016, IEEE Transactions on Computers.

A test pattern ordering algorithm for diagnosis with truncated fail data

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Reducing fault latency in concurrent on-line testing by using checking functions over internal lines

Irith Pomeranz, Sudhakar M. Reddy, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

On Compacting Test Response Data Containing Unknown Values

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2003, ICCAD.

SPADES: a simulator for path delay faults in sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

3-weight Pseudo-random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Trans. Computers.

Path Selection for Transition Path Delay Faults

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan

Irith Pomeranz, Sudhakar M. Reddy, 2006, IEEE Transactions on Computers.

On Dictionary-Based Fault Location in Digital Logic Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1997, IEEE Trans. Computers.

Pseudo random patterns using Markov sources for scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Nadir Z. Basturkmen, 2002, Proceedings. International Test Conference.

Vector restoration based static compaction of test sequences for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Generalization of independent faults for transition faults

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Worst-case and average-case analysis of n-detection test sets and test generation strategies

Irith Pomeranz, Sudhakar M. Reddy, 2007, IET Comput. Digit. Tech..

Partitioned n-detection test generation

Irith Pomeranz, Sudhakar M. Reddy, 2009, GLSVLSI '09.

An Improved Markov Source Design for Scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2003 .

Selecting High-Quality Delay Tests for Manufacturing Test and Debug

Irith Pomeranz, Srinivas Patil, Suriyaprakash Natarajan, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

On test program compaction

Irith Pomeranz, Matteo Sonza Reorda, Marco Gaudesi, 2015, 2015 20th IEEE European Test Symposium (ETS).

LOCSTEP: a logic-simulation-based test generation procedure

Irith Pomeranz, Sudhakar M. Reddy, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2000, IEEE Trans. Computers.

A diagnostic test generation procedure for synchronous sequential circuits based on test elimination

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Low-power test sets under test-related primary input constraints

Irith Pomeranz, 2013, Int. J. Crit. Comput. Based Syst..

Testability considerations in technology mapping

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

The effects of test compaction on fault diagnosis

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Improving the accuracy of defect diagnosis by adding and removing tests

Irith Pomeranz, 2016, IET Comput. Digit. Tech..

LFSR-Based Test Generation for Reduced Fail Data Volume

Irith Pomeranz, Srikanth Venkataraman, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2008, 2008 Asia and South Pacific Design Automation Conference.

Reconstruction of a functional test sequence for increased fault coverage

Irith Pomeranz, 2017, IET Comput. Digit. Tech..

Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion

Irith Pomeranz, Zvi Kohavi, I. Pomeranz, 1991, IEEE Trans. Computers.

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Effect of Communication in a Parallel Genetic Algorithm

Irith Pomeranz, Venkataramana Kommu, 1992, ICPP.

Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches

Irith Pomeranz, Sudhakar M. Reddy, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

On reset based functional broadside tests

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Delay fault models for VLSI circuits1

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1998, Integr..

Concurrent on-line testing of identical circuits through output comparison using non-identical input vectors

Irith Pomeranz, Sudhakar M. Reddy, 2004 .

On achieving complete testability of synchronous sequential circuits with synchronizing sequences

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, Proceedings., International Test Conference.

Low-complexity fault simulation under the multiple observation time testing approach

Irith Pomeranz, Sudhakar M. Reddy, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Test vector chains for increased resolution and reduced storage of diagnostic tests

Irith Pomeranz, 2012, IET Comput. Digit. Tech..

Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes

Irith Pomeranz, Sudhakar M. Reddy, Zhuo Zhang, 2007, 2007 Asia and South Pacific Design Automation Conference.

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults

Irith Pomeranz, 2019, 2019 IEEE International Test Conference (ITC).

MIX : A Test Generation System for

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1997 .

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1996, IEEE Trans. Computers.

Fail data reduction for diagnosis of scan chain faults under transparent-scan

Irith Pomeranz, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Test vector chains for increased targeted and untargeted fault coverage

Irith Pomeranz, Sudhakar M. Reddy, 2008, 2008 Asia and South Pacific Design Automation Conference.

An Enhanced Logic BIST Architecture for Online Testing

Irith Pomeranz, Sreejit Chakravarty, Narendra Devta-Prasanna, 2008, 2008 14th IEEE International On-Line Testing Symposium.

A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors

Irith Pomeranz, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A synthesis procedure for flexible logic functions

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings Design, Automation and Test in Europe.

Static Compaction by Merging of Seeds for LFSR-Based Test Generation

Irith Pomeranz, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Reducing the input test data volume under transparent scan

Irith Pomeranz, 2014, IET Comput. Digit. Tech..

The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality

Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 22nd International Conference on VLSI Design.

Improving the efficiency of static compaction based on chronological order enumeration of test sequences [logic testing]

Irith Pomeranz, Sudhakar M. Reddy, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

Irith Pomeranz, Bernd Becker, Ilia Polian, 2004 .

INCREDYBLE-TG: INCREmental DYnamic Test Generation Based on LEarning

Irith Pomeranz, Sudhakar M. Reddy, 1993, 30th ACM/IEEE Design Automation Conference.

An approach to test compaction for scan circuits that enhances at-speed testing

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

New Targets for Diagnostic Test Generation

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

COREL: a dynamic compaction procedure for synchronous sequential circuits with repetition and local static compaction

Irith Pomeranz, Sudhakar M. Reddy, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Reducing the storage requirements of a test sequence by using a background vector

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing

Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker, 2011, 2011 Design, Automation & Test in Europe.

Functional Broadside Templates for Low-Power Test Generation

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Enhancing Delay Fault Coverage through Low Power Segmented Scan

Irith Pomeranz, Bashir M. Al-Hashimi, Janusz Rajski, 2006, ETS.

Compact test sets for high defect coverage

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Path selection based on static timing analysis considering input necessary assignments

Irith Pomeranz, Bo Yao, Arani Sinha, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2009, TODE.

Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects

Irith Pomeranz, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests

Irith Pomeranz, 2011, 2011 Sixteenth IEEE European Test Symposium.

Test application time reduction for scan circuits using limited scan operations

Irith Pomeranz, Sudhakar M. Reddy, Yonsang Cho, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Resolution of Diagnosis Based on Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Aliasing Computation Using Fault Simulation with Fault Dropping

Irith Pomeranz, S. M. Reddy, 1995, IEEE Trans. Computers.

Weighted pseudo-random BIST for n-detection of single stuck-at faults

Irith Pomeranz, Sudhakar M. Reddy, Chaowen Yu, 2004, 13th Asian Test Symposium.

Fast Identification of Undetectable Transition Faults under Functional Broadside Tests

Irith Pomeranz, 2012, IEEE Transactions on Computers.

Detectability of internal bridging faults in scan chains

Irith Pomeranz, Sreejit Chakravarty, Narendra Devta-Prasanna, 2009, 2009 Asia and South Pacific Design Automation Conference.

Test data compression based on output dependence

Irith Pomeranz, Sudhakar M. Reddy, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Innovative practices session 10C: Advances in DFT and compression

Irith Pomeranz, Rohit Kapur, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Selecting Close-to-Functional Path Delay Faults for Test Generation

Irith Pomeranz, 2020, 2020 IEEE International Test Conference (ITC).

On the Computation of Common Test Data for Broadside and Skewed-Load Tests

Irith Pomeranz, 2012, IEEE Transactions on Computers.

LFSR-Based Test Generation for Path Delay Faults

Irith Pomeranz, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes

Irith Pomeranz, Sudhakar M. Reddy, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Computation of Seeds for LFSR-Based Diagnostic Test Generation

Irith Pomeranz, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

Optimizing SOC Test Resources using Dual Sequences

Irith Pomeranz, Sudhakar M. Reddy, Chris C. N. Chu, 2003, VLSI-SOC.

Defect diagnosis based on DFM guidelines

Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman, 2010, 2010 28th VLSI Test Symposium (VTS).

New procedures for identifying undetectable and redundant faults in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Definition and application of approximate necessary assignments

Irith Pomeranz, Sudhakar M. Reddy, 2009, GLSVLSI '09.

On validating data hold times for flip-flops in sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2007, Electron. Notes Theor. Comput. Sci..

VERSE: a vector replacement procedure for improving test compaction in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults

Irith Pomeranz, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Static Test Compaction for Scan-Based Designs to Reduce Test Application Time

Irith Pomeranz, Sudhakar M. Reddy, 2000, J. Electron. Test..

On the Generation of Weights for Weighted Pseudo Random Testing

Irith Pomeranz, Sudhakar M. Reddy, 1993, The Sixth International Conference on VLSI Design.

On Reducing Circuit Malfunctions Caused by Soft Errors

Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

On the generation of scan-based test sets with reachable states for testing under functional operation conditions

Irith Pomeranz, 2004, Proceedings. 41st Design Automation Conference, 2004..

A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion

Irith Pomeranz, Zvi Kohavi, I. Pomeranz, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage

Irith Pomeranz, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Functional Broadside Tests Under Broadcast Scan

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On n-detection test sequences for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits

Irith Pomeranz, Sudhakar M. Reddy, 1999, IEEE Trans. Computers.

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Non-Masking Non-Robust Tests for Path Delay Faults

Irith Pomeranz, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

Static compaction for two-pattern test sets

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1995, Proceedings of the Fourth Asian Test Symposium.

Selecting Functional Test Sequences for Defect Diagnosis

Irith Pomeranz, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Static test compaction for scan-based designs to reduce test application time

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Diagnosis of path delay faults based on low-coverage tests

Irith Pomeranz, Sudhakar M. Reddy, 2010, IET Comput. Digit. Tech..

On methods to match a test pattern generator to a circuit-under-test

Irith Pomeranz, Sudhakar M. Reddy, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults

Irith Pomeranz, 2011, 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing.

Recovery during concurrent on-line testing of identical circuits

Irith Pomeranz, Sudhakar M. Reddy, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Improving the proportion of at-speed tests in scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Forward-looking fault simulation for improved static compaction

Irith Pomeranz, Sudhakar M. Reddy, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Selection of Primary Output Vectors to Observe Under Multicycle Tests

Irith Pomeranz, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On generating test sets that remain valid in the presence of undetected faults

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings Great Lakes Symposium on VLSI.

On testing of non-isolated embedded legacy cores and their surround logic

Yervant Zorian, Irith Pomeranz, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A definition of the number of detections for faults with single tests in a compact scan-based test set

Irith Pomeranz, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Reset and partial-reset-based functional broadside tests

Irith Pomeranz, Sudhakar M. Reddy, 2012, IET Comput. Digit. Tech..

COMPACTEST: a method to generate compact test sets for combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the use of reset to increase the testability of interconnected finite-state machines

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Built-in test generation for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1997, ICCAD 1997.

An Adjacent Switching Activity Metric under Functional Broadside Tests

Irith Pomeranz, 2013, IEEE Transactions on Computers.

On tests to detect via opens in digital CMOS circuits

Irith Pomeranz, Sudhakar M. Reddy, Chen Liu, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Fault isolation for nonisolated blocks

Yervant Zorian, Irith Pomeranz, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests

Irith Pomeranz, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Observation Points on State Variables for the Compaction of Multicycle Tests

Irith Pomeranz, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set

Irith Pomeranz, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On test generation for interconnected finite-state machines-the input sequence propagation problem

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

Diagnostic Test Generation Based on Subsets of Faults

Irith Pomeranz, Sudhakar M. Reddy, 2007, 12th IEEE European Test Symposium (ETS'07).

Simulation based test generation for scan designs

Irith Pomeranz, Sudhakar M. Reddy, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

On Testing Delay Faults In Macro-based Combinational Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1994, IEEE/ACM International Conference on Computer-Aided Design.

A-Diagnosis: A Complement to Z-Diagnosis

Irith Pomeranz, Sudhakar M. Reddy, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis

Irith Pomeranz, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Pattern sensitivity: a property to guide test generation for combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

On the generation of small dictionaries for fault location

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2001, J. Syst. Archit..

On generating compact test sequences for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1995, Proceedings of EURO-DAC. European Design Automation Conference.

On the Saturation of $n$-Detection Test Generation by Different Definitions With Increased $n$

Irith Pomeranz, Sudhakar M. Reddy, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Built-In Self-Test Method for Diagnosis of

Irith Pomeranz, Sudhakar M. Reddy, 2001 .

Static test compaction for transition faults under the hazard-based detection conditions

Irith Pomeranz, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation

Irith Pomeranz, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FPGA technology mapping

Irith Pomeranz, Venkataramana Kommu, 1999 .

On determining symmetries in inputs of logic circuits

Irith Pomeranz, Sudhakar M. Reddy, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Computing Two-Pattern Test Cubes for Transition Path Delay Faults

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Testing for systematic defects based on DFM guidelines

Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman, 2007, 2007 IEEE International Test Conference.

Properties of maximally dominating faults

Irith Pomeranz, Sudhakar M. Reddy, 2004, 13th Asian Test Symposium.

On Selecting Testable Paths in Scan Designs

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 2003, J. Electron. Test..

On Improving Fault Diagnosis for Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 1994, 31st Design Automation Conference.

Transient-fault recovery for chip multiprocessors

Irith Pomeranz, T. N. Vijaykumar, Mohamed A. Gomaa, 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 23rd International Conference on VLSI Design.

Low-Power Test Generation by Merging of Functional Broadside Test Cubes

Irith Pomeranz, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FaultHound: Value-locality-based soft-fault tolerance

Irith Pomeranz, Nitin, T. N. Vijaykumar, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

On the generation of small dictionaries for fault location

Irith Pomeranz, Sudhakar M. Reddy, 1992, ICCAD.

On synchronizable circuits and their synchronizing sequences

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

MIX: a test generation system for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1998, Proceedings Eleventh International Conference on VLSI Design.

PROPTEST: a property-based test generator for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads

Irith Pomeranz, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests

Irith Pomeranz, Srikanth Venkataraman, Brady Benware, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Fault simulation with test switching for static test compaction

Irith Pomeranz, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

POSTT: Path-oriented static test compaction for transition faults in scan circuits

Irith Pomeranz, 2017, 2017 IEEE International Test Conference (ITC).

Enhanced untestable path analysis using edge graphs

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 2000, Proceedings of the Ninth Asian Test Symposium.

Exact computation of maximally dominating faults and its application to n-detection tests

Irith Pomeranz, Bernd Becker, Ilia Polian, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Test compaction methods for transition faults under transparent-scan

Irith Pomeranz, Sudhakar M. Reddy, 2009, IET Comput. Digit. Tech..

A delay fault model for at-speed fault simulation and test generation

Irith Pomeranz, Sudhakar M. Reddy, 2006, ICCAD.

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test

Irith Pomeranz, Sudhakar M. Reddy, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits

Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri, 1993, 30th ACM/IEEE Design Automation Conference.

Max-Fill: A method to generate high quality delay tests

Irith Pomeranz, Sudhakar M. Reddy, Xiaoxin Fan, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Improving the Detectability of Resistive Open Faults in Scan Cells

Irith Pomeranz, Sudhakar M. Reddy, Sreejit Chakravarty, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

New procedures to identify redundant stuck-at faults and removal of redundant logic

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Two-dimensional partially functional broadside tests

Irith Pomeranz, Sudhakar M. Reddy, 2011, IET Comput. Digit. Tech..

Functional Broadside Test Generation Using a Commercial ATPG Tool

Irith Pomeranz, Bo Yao, Xijiang Lin, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks

Irith Pomeranz, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests

Irith Pomeranz, 2012, IEEE Transactions on Computers.

Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation

Irith Pomeranz, 2019, 2019 IEEE International Test Conference (ITC).

Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths

Irith Pomeranz, Sudhakar M. Reddy, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Properties of output sequences and their use in guiding property-based test generation for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Experimental results of forward-looking reverse order fault simulation on industrial circuits with scan

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 2001, Proceedings 10th Asian Test Symposium.

On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2008, 2008 Design, Automation and Test in Europe.

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic

Irith Pomeranz, Sudhakar M. Reddy, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LFSR-based generation of boundary-functional broadside tests

Irith Pomeranz, 2020, IET Comput. Digit. Tech..

On removing redundant faults in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Transient-fault recovery using simultaneous multithreading

Irith Pomeranz, T. N. Vijaykumar, Karl Cheng, 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

Dominance based analysis for large volume production fail diagnosis

Irith Pomeranz, Sudhakar M. Reddy, Enamul Amyeen, 2006, 24th IEEE VLSI Test Symposium.

Substituting transition faults with path delay faults as a basic delay fault model

Irith Pomeranz, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

On-chip compression of output responses with unknown values using lfsr reseeding

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Test generation for synchronous sequential circuits based on fault extraction

Irith Pomeranz, Sudhakar M. Reddy, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing of Fault-Tolerant Hardware

Irith Pomeranz, Sudhakar M. Reddy, 1991, Fault-Tolerant Computing Systems.

Input test data volume reduction based on test vector chains

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 15th IEEE European Test Symposium.

Random Test Generation With Input Cube Avoidance

Irith Pomeranz, Sudhakar M. Reddy, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Trans. Very Large Scale Integr. Syst..

Fault location based on circuit partitioning

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults

Irith Pomeranz, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Fault Collapsing for Transition Faults Using Extended Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, 2006, Eleventh IEEE European Test Symposium (ETS'06).

On achieving zero aliasing for modeled faults

Irith Pomeranz, Sudhakar M. Reddy, R. Tangirala, 1992, [1992] Proceedings The European Conference on Design Automation.

Forming multi-cycle tests for delay faults by concatenating broadside tests

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 28th VLSI Test Symposium (VTS).

EXOP (Extended Operation): A new logical fault model for digital circuits

Irith Pomeranz, Sudhakar M. Reddy, 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume

Irith Pomeranz, M. Enamul Amyeen, 2020 .

The minimum test set problem for circuits with nonreconvergent fanout

Irith Pomeranz, Zvi Kohavi, 1991, J. Electron. Test..

A test application scheme for embedded full-scan circuits to reduce testing costs

Irith Pomeranz, Sudhakar M. Reddy, 1992, Proceedings First Asian Test Symposium (ATS `92).

$z$-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On Compacting Test Response Data Containing Unknown Values

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2003, ICCAD 2003.

On Undetectable Faults and Fault Diagnosis

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enhancing Delay Fault Coverage through Low Power Segmented Scan

Irith Pomeranz, Sudhakar M. Reddy, Bashir M. Al-Hashimi, 2006, Eleventh IEEE European Test Symposium (ETS'06).

COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS

Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy, 1991, 1991, Proceedings. International Test Conference.

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits

Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy, 1992, ICCAD.

Forming N-detection test sets from one-detection test sets without test generation

Irith Pomeranz, Sudhakar M. Reddy, 2005, IEEE International Conference on Test, 2005..

Undetectable transition faults under broadside tests with constant primary input vectors

Irith Pomeranz, 2012, IET Comput. Digit. Tech..

On the use of random limited-scan to improve at-speed randompattern testing of scan circuits

Irith Pomeranz, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scan Shift Power of Functional Broadside Tests

Irith Pomeranz, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Built-in generation of multi-cycle broadside tests

Irith Pomeranz, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Functional test generation for delay faults in combinational circuits

Irith Pomeranz, S. M. Reddy, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Using piecewise-functional broadside tests for functional broadside test compaction

Irith Pomeranz, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests

Irith Pomeranz, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

LFSR-Based Generation of Multicycle Tests

Irith Pomeranz, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TEMPLATES: a test generation procedure for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Close-to-Functional Broadside Tests With a Safety Margin

Irith Pomeranz, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reverse Low-Power Broadside Tests

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On minimizing the number of test points needed to achieve complete robust path delay fault testability

Irith Pomeranz, Uwe Sparmann, Prasanti Uppaluri, 1996, Proceedings of 14th VLSI Test Symposium.

Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults

Irith Pomeranz, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On diagnosis and correction of design errors

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Battery-aware dynamic voltage scaling in multiprocessor embedded system

Irith Pomeranz, Bashir M. Al-Hashimi, Sudhakar M. Reddy, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Masking of unknown output values during output response compression by using comparison units

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2004, IEEE Transactions on Computers.

Generation of Functional Broadside Tests for Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On interconnecting circuits with multiple scan chains for improved test data compression

Irith Pomeranz, Sudhakar M. Reddy, 2004, 17th International Conference on VLSI Design. Proceedings..

A test generation procedure for avoiding the detection of functionally redundant transition faults

Irith Pomeranz, Sudhakar M. Reddy, Hangkyu Lee, 2006, 24th IEEE VLSI Test Symposium.

Compact test generation for bridging faults under I/sub DDQ/ testing

Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults

Irith Pomeranz, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2009, IEEE Transactions on Dependable and Secure Computing.

Dynamic test compaction for a random test generation procedure with input cube avoidance

Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 Asia and South Pacific Design Automation Conference.

Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences

Irith Pomeranz, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Built-in generation of weighted test sequences for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2000, DATE '00.

Reducing test-data volume using random-testable and periodic-testable scan chains in circuits with multiple scan chains

Irith Pomeranz, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

On test generation for interconnected finite-state machines-the output sequence justification problem

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1996, Proceedings ED&TC European Design and Test Conference.

Scan-BIST based on transition probabilities

Irith Pomeranz, 2004, Proceedings. 41st Design Automation Conference, 2004..

Invariant States and Redundant Logic in Synchronous Sequential Circuits

Irith Pomeranz, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Sequential Test Generation Based on Preferred Primary Input Cubes

Irith Pomeranz, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A low power pseudo-random BIST technique

Irith Pomeranz, Sudhakar M. Reddy, Nadir Z. Basturkmen, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

On Test Generation With Test Vector Improvement

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-cycle broadside tests with runs of constant primary input vectors

Irith Pomeranz, 2014, IET Comput. Digit. Tech..

Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

Broadside and Functional Broadside Tests for Partial-Scan Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Logic Diagnosis with Hybrid Fail Data

Irith Pomeranz, M. Enamul Amyeen, I. Pomeranz, 2020, ACM Trans. Design Autom. Electr. Syst..

On the use of multi-cycle tests for storage of two-cycle broadside tests

Irith Pomeranz, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

On Close-to-Functional Test Sequences

Irith Pomeranz, 2018, 2018 IEEE International Test Conference (ITC).

Enhanced genetic algorithms in constrained search spaces with emphasis in parallel environments

Irith Pomeranz, Venkataramana Kommu, 1993 .

Fault diagnosis and fault model aliasing

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Forming N-detection test sets without test generation

Irith Pomeranz, Sudhakar M. Reddy, 2007, TODE.

Fault isolation using tests for non-isolated blocks

Yervant Zorian, Irith Pomeranz, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests

Irith Pomeranz, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Non-Uniform Coverage by $n$-Detection Test Sets

Irith Pomeranz, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Defect aware test patterns

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2005, Design, Automation and Test in Europe.

Unknown Output Values of Faulty Circuits and Output Response Compaction

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On undetectable faults in partial scan circuits using transparent-scan

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Test Sequences with Reduced and Increased Switching Activity

Irith Pomeranz, Sudhakar M. Reddy, 2010, J. Low Power Electron..

Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences

Irith Pomeranz, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Vector-restoration-based static compaction using random initial omission

Irith Pomeranz, Sudhakar M. Reddy, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells

Irith Pomeranz, Sudhakar M. Reddy, Sreejit Chakravarty, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

A unified fault model and test generation procedure for interconnect opens and bridges

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2005, European Test Symposium (ETS'05).

On testing delay faults in macro-based combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, 1994, ICCAD.

Worst-case and average-case analysis of n-detection test sets

Irith Pomeranz, Sudhakar M. Reddy, 2005, Design, Automation and Test in Europe.

A postprocessing procedure of test enrichment for path delay faults

Irith Pomeranz, Sudhakar M. Reddy, 2004, 13th Asian Test Symposium.

Static test compaction for synchronous sequential circuits based on vector restoration

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines

Irith Pomeranz, Sudhakar M. Reddy, 2000, IEEE Trans. Computers.

On diagnosis and correction of design errors

Irith Pomeranz, Sudhakar M. Reddy, 1993, ICCAD.

Theorems for identifying undetectable faults in partial-scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Improved$n$-Detection Test Sequences Under Transparent Scan

Irith Pomeranz, Sudhakar M. Reddy, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Computers.

Built-in generation of multicycle functional broadside tests with observation points

Irith Pomeranz, 2013, TODE.

Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault equivalence identification using redundancy information and static and dynamic extraction

Irith Pomeranz, Vamsi Boppana, W. Kent Fuchs, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences

Irith Pomeranz, Sudhakar M. Reddy, 2006, 2006 IEEE International Test Conference.

Functional test generation for delay faults in combinational circuits

Irith Pomeranz, Sudhakar M. Reddy, 1995, TODE.

Static test compaction for multiple full-scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2003, Proceedings 21st International Conference on Computer Design.

Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage

Irith Pomeranz, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Metric for the ability of functional capture cycles to ensure functional operation conditions

Irith Pomeranz, 2017, IET Comput. Digit. Tech..

Functional Broadside Tests with Different Levels of Reachability

Irith Pomeranz, Sudhakar M. Reddy, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A scan BIST generation method using a markov source and partial bit-fixing

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2003, DAC '03.

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences

Irith Pomeranz, 2015, TODE.

On-chip Generation of the Second Primary Input Vectors of Broadside Tests

Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A low power pseudo-random BIST technique

Irith Pomeranz, Sudhakar M. Reddy, Nadir Z. Basturkmen, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

Built-in test generation for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

On generating high quality tests for transition faults

Irith Pomeranz, Sudhakar M. Reddy, Yun Shao, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TSV and DFT cost aware circuit partitioning for 3D-SOCs

Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan

Irith Pomeranz, Sudhakar M. Reddy, 2011, J. Low Power Electron..

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999 .

Functional Broadside Tests for Multistep Defect Diagnosis

Irith Pomeranz, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On Synthesis-for-Testability of Combinational Logic Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1995, 32nd Design Automation Conference.

Balancing the Numbers of Detected Faults for Improved Test Set Quality

Irith Pomeranz, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Broadside and Skewed-Load Tests Under Primary Input Constraints

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Scan-Based Tests with Low Switching Activity

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2007, IEEE Design & Test of Computers.

Irith Pomeranz, Sudhakar M. Reddy, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Dynamic test compaction for synchronous sequential circuits using static compaction techniques

Irith Pomeranz, Sudhakar M. Reddy, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure

Irith Pomeranz, Srikanth Venkataraman, Shraddha Bodhe, 2017, 2017 IEEE International Test Conference (ITC).

Path delay fault test generation for standard scan designs using state tuples

Irith Pomeranz, Sudhakar M. Reddy, Yun Shao, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Interconnect-aware tests to complement gate-exhaustive tests

Irith Pomeranz, Srikanth Venkataraman, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator

Irith Pomeranz, Sudhakar M. Reddy, Chaowen Yu, 2005, 14th Asian Test Symposium (ATS'05).

Fault equivalence identification in combinational circuits using implication and evaluation techniques

Irith Pomeranz, Vamsi Boppana, W. Kent Fuchs, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Target Faults for Test Compaction Based on Multicycle Tests

Irith Pomeranz, 2020, ACM Trans. Design Autom. Electr. Syst..

Test Modification for Reduced Volumes of Fail Data

Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, 2017, ACM Trans. Design Autom. Electr. Syst..

Storage-Based Built-In Self-Test for Gate-Exhaustive Faults

Irith Pomeranz, 2020 .

Generation of Mixed Test Sets for Transition Faults

Irith Pomeranz, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2010, IEEE Transactions on Computers.

Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences

Irith Pomeranz, I. Pomeranz, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Incomplete Tests for Undetectable Faults to Improve Test Set Quality

Irith Pomeranz, 2019, ACM Trans. Design Autom. Electr. Syst..

Scan BIST targeting transition faults using a Markov source

Irith Pomeranz, Sudhakar M. Reddy, Hangkyu Lee, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Test generation for synchronous sequential circuits to reduce storage requirements

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults

Irith Pomeranz, I. Pomeranz, 2017, ACM Trans. Design Autom. Electr. Syst..

An approach for improving the levels of compaction achieved by vector omission

Irith Pomeranz, Sudhakar M. Reddy, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

ACTIV-LOCSTEP: a test generation procedure based on logic simulation and fault activation

Irith Pomeranz, Sudhakar M. Reddy, 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

A new approach to test generation and test compaction for scan circuits

Irith Pomeranz, Sudhakar M. Reddy, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

On the Detectability of Scan Chain Internal Faults An Industrial Case Study

Irith Pomeranz, Sreejit Chakravarty, Narendra Devta-Prasanna, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Selecting state variables for improved on-line testability through output response comparison of identical circuits

Irith Pomeranz, Sudhakar M. Reddy, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Globally Functional Transparent-Scan Sequences

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences

Irith Pomeranz, Sudhakar M. Reddy, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Static test compaction for circuits with multiple independent scan chains

Irith Pomeranz, 2016, IET Comput. Digit. Tech..

A Low Power Pseudo-Random BIST Technique

Irith Pomeranz, Sudhakar M. Reddy, Nadir Z. Basturkmen, 2003, J. Electron. Test..

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

Irith Pomeranz, Sudhakar M. Reddy, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Conflict driven techniques for improving deterministic test pattern generation

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, ICCAD 2002.

A divide-and-conquer approach to test generation for large synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1998, IEEE Trans. Computers.

Classification of Faults in Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1993, IEEE Trans. Computers.

Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains

Irith Pomeranz, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction

Irith Pomeranz, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Test and non-test cubes for diagnostic test generation based on merging of test cubes

Irith Pomeranz, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A scalable method for the generation of small test sets

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

Irith Pomeranz, Sudhakar M. Reddy, 2003, ICCAD 2003.

On the characterization of hard-to-detect bridging faults

Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A diagnostic test generation procedure for combinational circuits based on test elimination

Irith Pomeranz, W. Kent Fuchs, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Fault Diagnosis under Transparent-Scan

Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 Asian Test Symposium.

On Error Correction In Macro-based Circuits

Irith Pomeranz, S. M. Reddy, S. Reddy, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Test-point insertion to enhance test compaction for scan designs

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceeding International Conference on Dependable Systems and Networks. DSN 2000.

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2006, 2006 IEEE International Test Conference.

On double transition faults as a delay fault model

Janak H. Patel, Irith Pomeranz, Sudhakar M. Reddy, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

On Finding Don't Cares in Test Sequences for Sequential Circuits

Irith Pomeranz, Yuzo Takamatsu, Yoshinobu Higami, 2006, IEICE Trans. Inf. Syst..

Full scan fault coverage with partial scan

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity

Irith Pomeranz, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault simulation based test generation for combinational circuits using dynamically selected subcircuits

Irith Pomeranz, Sudhakar M. Reddy, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Generalized Test Generation Procedure for Path Delay Faults

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1998, FTCS.

Restoration-Based Merging of Functional Test Sequences

Irith Pomeranz, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points

Irith Pomeranz, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Random limited-scan to improve random pattern testing of scan circuits

Irith Pomeranz, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs

Irith Pomeranz, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

Test Compaction for Transition Faults under Transparent-Scan

Irith Pomeranz, Sudhakar M. Reddy, 2006, Proceedings of the Design Automation & Test in Europe Conference.

On achieving a complete fault coverage for sequential machines using the transition fault model

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1991, 28th ACM/IEEE Design Automation Conference.

Two-Dimensional Static Test Compaction for Functional Test Sequences

Irith Pomeranz, I. Pomeranz, 2015, IEEE Transactions on Computers.

Extended Transparent-Scan

Irith Pomeranz, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

N-Detection Test Sets for Circuits with Multiple Independent Scan Chains

Irith Pomeranz, 2016, TODE.

Design-for-Testability for Functional Broadside Tests under Primary Input Constraints

Irith Pomeranz, 2016, TODE.

On static test compaction and test pattern ordering for scan designs

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

Irith Pomeranz, Sudhakar M. Reddy, 2003, ICCAD.

Reducing the switching activity of test sequences under transparent-scan

Irith Pomeranz, Sudhakar M. Reddy, 2011, TODE.

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation

Irith Pomeranz, 2015, ACM Trans. Design Autom. Electr. Syst..

Reverse-order-restoration-based static test compaction for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Concurrent on-line testing of identical circuits through output comparison using non-identical input vectors

Irith Pomeranz, Sudhakar M. Reddy, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Selection of a fault model for fault diagnosis based on unique responses

Irith Pomeranz, S. M. Reddy, 2009 .

Signal-Transition Patterns of Functional Broadside Tests

Irith Pomeranz, 2013, IEEE Transactions on Computers.

Test Compaction Under Bounded Transparent-Scan

Irith Pomeranz, I. Pomeranz, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

On diagnosis and diagnostic test generation for pattern-dependenttransition faults

Irith Pomeranz, Sudhakar M. Reddy, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests

Irith Pomeranz, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Diagnostic Test Sets with Increased Switching Activity for Transition Faults

Irith Pomeranz, 2013, J. Low Power Electron..

On reducing peak current and power during test

Irith Pomeranz, Sudhakar M. Reddy, Wei Li, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Switching Activity as a Test Compaction Heuristic for Transition Faults

Irith Pomeranz, Sudhakar M. Reddy, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The accidental detection index as a fault ordering heuristic for full-scan circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2005, Design, Automation and Test in Europe.

State persistence: a property for guiding test generation

Irith Pomeranz, Sudhakar M. Reddy, 2009, GLSVLSI '09.

On Test Compaction of Broadside and Skewed-Load Test Cubes

Irith Pomeranz, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Built-in generation of functional broadside tests

Irith Pomeranz, 2011, 2011 Design, Automation & Test in Europe.

On the saturation of n-detection test sets with increased n

Irith Pomeranz, Sudhakar M. Reddy, 2007, 2007 IEEE International Test Conference.

N-detection under transparent-scan

Irith Pomeranz, 2005, Proceedings. 42nd Design Automation Conference, 2005..

On test application time and defect detection capabilities of test sets for scan designs

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceedings 2000 International Conference on Computer Design.

On finding undetectable and redundant faults in synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceedings IEEE European Test Workshop.

State assignment using input/output functions

Irith Pomeranz, Kwang-Ting Cheng, K. Cheng, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Test generation for multiple state-table faults in finite-state machines

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

On achieving complete fault coverage for sequential machines

Irith Pomeranz, Sudhakar M. Reddy, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient non-enumerative method to estimate path delay fault coverage

Irith Pomeranz, Sudhakar M. Reddy, 1992, ICCAD.

Double–Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Aliasing computation using fault simulation with fault dropping

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2003, Proceedings 21st International Conference on Computer Design.

Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy

Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

N-distinguishing Tests for Enhanced Defect Diagnosis

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 Asian Test Symposium.

On-chip generation of primary input sequences for multicycle functional broadside tests

Irith Pomeranz, 2018, IET Comput. Digit. Tech..

A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

Static Test Data Volume Reduction Using Complementation or Modulo-$M$ Addition

Irith Pomeranz, Sudhakar M. Reddy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Selecting target bridging faults for uniform circuit coverage

Irith Pomeranz, 2017, 2017 IEEE International Test Conference (ITC).

On codeword testing of two-rail and parity TSC checkers

Irith Pomeranz, Sudhakar M. Reddy, Rahul Jain, 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set

Irith Pomeranz, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Improved built-in test pattern generators based on comparison units for synchronous sequential circuits

Irith Pomeranz, Sudhakar M. Reddy, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

A distance-based test cube merging procedure for compatible and incompatible test cubes

Irith Pomeranz, 2014, 2014 19th IEEE European Test Symposium (ETS).

Fault diagnosis based on parameters of output responses

Irith Pomeranz, Sudhakar M. Reddy, 2000, Proceedings. 2000 Pacific Rim International Symposium on Dependable Computing.

On undetectable faults in partial scan circuits

Irith Pomeranz, Sudhakar M. Reddy, S. Reddy, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

No Free Lunch in Soft Error Protection

Irith Pomeranz, Ilia Polian, Bernd Becker, 2008 .

Built-in generation of functional broadside tests considering primary input constraints

Irith Pomeranz, Bo Yao, Enamul Amyeen, 2014, GLSVLSI '14.

Transient-Fault Recovery for Chip Multiprocessors

Irith Pomeranz, T. N. Vijaykumar, Mohamed A. Gomaa, 2003, IEEE Micro.

Test compaction by test cube merging for four-way bridging faults

Irith Pomeranz, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Improving the accuracy of defect diagnosis by considering reduced diagnostic information

Irith Pomeranz, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests

Irith Pomeranz, 2020 .

Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests

Irith Pomeranz, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fault dictionary compression and equivalence class computation for sequential circuits

Irith Pomeranz, W. Kent Fuchs, P. G. Ryan, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Multicycle Tests with Fault Detection Test Data for Improved Logic Diagnosis

Irith Pomeranz, 2021 .

Static Test Compaction using Independent Suffixes of a Transparent-Scan Sequence

Irith Pomeranz, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults

Irith Pomeranz, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests

Irith Pomeranz, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation

Irith Pomeranz, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Compact Set of LFSR Seeds for Diagnostic Tests

Irith Pomeranz, 2021, 2021 IEEE 39th VLSI Test Symposium (VTS).

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors

Irith Pomeranz, 2021, ACM Trans. Design Autom. Electr. Syst..

Zoom-In Feature for Storage-Based Logic Built-In Self-Test

Irith Pomeranz, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Covering Test Holes of Functional Broadside Tests

Irith Pomeranz, 2021, ACM Trans. Design Autom. Electr. Syst..

Test Compaction by Backward and Forward Extension of Multicycle Tests

Irith Pomeranz, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults

Irith Pomeranz, 2021 .

Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests

Irith Pomeranz, 2021, 2021 IEEE 30th Asian Test Symposium (ATS).

Padding of LFSR Seeds for Reduced Input Test Data Volume

Irith Pomeranz, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test generation for path delay faults based on learning

Irith Pomeranz, Sudhakar M. Reddy, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

An efficient non-enumerative method to estimate path delay fault coverage

Irith Pomeranz, Sudhakar M. Reddy, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.