Mohd-Shahiman Sulaiman

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Manoj Sachdev, Tan Kok-Siang, Mohd-Shahiman Sulaiman, 2007 .

A fast-lock delay-locked loop architecture with improved precharged PFD

Mohd-Shahiman Sulaiman, Soh Lip-Kai, Zubaida Yusoff, 2008 .

A low-power high-speed 1-Mb CMOS SRAM

Tan Soon-Hwei, Mohd-Shahiman Sulaiman, Loh Poh-Yee, 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

Design of high-speed clock and data recovery circuits

Manoj Sachdev, Tan Kok-Siang, Mohd-Shahiman Sulaiman, 2007 .