R. Kubota

Low-temperature metal/ON/HSG-cylinder capacitor process for high density embedded DRAMs

K. Tokunaga, Y. Takaishi, M. Hamada, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

I. Naritake, M. Togo, T. Sugibayashi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

T. Sakoh, M. Sakao, M. Hamada, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).